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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
37#define CONFIG_4xx 1 /* ...member of PPC405 family */
38#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
39#define CONFIG_W7OLMC 1 /* ...specifically an LMC */
40
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
42
wdenkc837dcb2004-01-20 23:12:12 +000043#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
44#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050045#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
wdenke2211742002-11-02 23:30:20 +000046
47#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
48
49#define CONFIG_BAUDRATE 9600
50#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
51
52#if 1
53#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
54#else
55#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
56#endif
57
58#undef CONFIG_BOOTARGS
59
60#define CONFIG_LOADADDR F0080000
61
62#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
63#define CONFIG_OVERWRITE_ETHADDR_ONCE
64#define CONFIG_IPADDR 192.168.1.1
65#define CONFIG_NETMASK 255.255.255.0
66#define CONFIG_SERVERIP 192.168.1.2
67
68#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
wdenke2211742002-11-02 23:30:20 +000070
Ben Warren96e21f82008-10-27 23:50:15 -070071#define CONFIG_PPC4xx_EMAC
wdenke2211742002-11-02 23:30:20 +000072#define CONFIG_MII 1 /* MII PHY management */
73#define CONFIG_PHY_ADDR 0 /* PHY address */
Ben Warren18cc7af2009-04-28 16:50:53 -070074#define CONFIG_NET_MULTI
wdenke2211742002-11-02 23:30:20 +000075
76#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
77
Jon Loeligera5562902007-07-08 15:31:57 -050078/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050079 * BOOTP options
80 */
81#define CONFIG_BOOTP_BOOTFILESIZE
82#define CONFIG_BOOTP_BOOTPATH
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85
86
87/*
Jon Loeligera5562902007-07-08 15:31:57 -050088 * Command line configuration.
89 */
90#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +000091
Jon Loeligera5562902007-07-08 15:31:57 -050092#define CONFIG_CMD_PCI
93#define CONFIG_CMD_IRQ
94#define CONFIG_CMD_ASKENV
95#define CONFIG_CMD_DHCP
96#define CONFIG_CMD_BEDBUG
97#define CONFIG_CMD_DATE
98#define CONFIG_CMD_I2C
99#define CONFIG_CMD_EEPROM
100#define CONFIG_CMD_ELF
101#define CONFIG_CMD_BSP
102#define CONFIG_CMD_REGINFO
wdenke2211742002-11-02 23:30:20 +0000103
104#undef CONFIG_WATCHDOG /* watchdog disabled */
105#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
106
107#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
wdenkdb2f721f2003-03-06 00:58:30 +0000108#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
wdenke2211742002-11-02 23:30:20 +0000109/*
110 * Miscellaneous configurable options
111 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_LONGHELP /* undef to save memory */
113#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
114#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
115#ifdef CONFIG_SYS_HUSH_PARSER
116#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenke2211742002-11-02 23:30:20 +0000117#endif
Jon Loeligera5562902007-07-08 15:31:57 -0500118#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000120#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000122#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
124#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
125#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
128#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000129
Stefan Roese550650d2010-09-20 16:05:31 +0200130#define CONFIG_CONS_INDEX 1 /* Use UART0 */
131#define CONFIG_SYS_NS16550
132#define CONFIG_SYS_NS16550_SERIAL
133#define CONFIG_SYS_NS16550_REG_SIZE 1
134#define CONFIG_SYS_NS16550_CLK get_serial_clock()
135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
137#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
138#define CONFIG_SYS_BASE_BAUD 384000
wdenke2211742002-11-02 23:30:20 +0000139
140
141/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_BAUDRATE_TABLE {9600}
wdenke2211742002-11-02 23:30:20 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
145#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
wdenke2211742002-11-02 23:30:20 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000148
149/*-----------------------------------------------------------------------
150 * PCI stuff
151 *-----------------------------------------------------------------------
152 */
153#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
154#define PCI_HOST_FORCE 1 /* configure as pci host */
155#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
156
157
158#define CONFIG_PCI /* include pci support */
159#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
160#define CONFIG_PCI_PNP /* pci plug-and-play */
161/* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
163#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
164#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
165#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
166#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
167#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
168#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
169#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenke2211742002-11-02 23:30:20 +0000170
171/*-----------------------------------------------------------------------
172 * Set up values for external bus controller
173 * used by cpu_init.c
174 *-----------------------------------------------------------------------
175 */
176 /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
177#undef CONFIG_USE_PERWE
178
179/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenke2211742002-11-02 23:30:20 +0000181
182/* bank 0 is boot flash */
183/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
wdenke2211742002-11-02 23:30:20 +0000185/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
wdenke2211742002-11-02 23:30:20 +0000187
188/* bank 1 is main flash */
189/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_EBC_PB1AP 0x05850240
wdenke2211742002-11-02 23:30:20 +0000191/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_EBC_PB1CR 0xF00FC000
wdenke2211742002-11-02 23:30:20 +0000193
194/* bank 2 is RTC/NVRAM */
195/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_EBC_PB2AP 0x03000440
wdenke2211742002-11-02 23:30:20 +0000197/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_EBC_PB2CR 0xFC018000
wdenke2211742002-11-02 23:30:20 +0000199
200/* bank 3 is FPGA 0 */
201/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_EBC_PB3AP 0x02000400
wdenke2211742002-11-02 23:30:20 +0000203/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_EBC_PB3CR 0xFD01A000
wdenke2211742002-11-02 23:30:20 +0000205
206/* bank 4 is FPGA 1 */
207/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_EBC_PB4AP 0x02000400
wdenke2211742002-11-02 23:30:20 +0000209/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_EBC_PB4CR 0xFD11A000
wdenke2211742002-11-02 23:30:20 +0000211
212/* bank 5 is FPGA 2 */
213/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_EBC_PB5AP 0x02000400
wdenke2211742002-11-02 23:30:20 +0000215/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_EBC_PB5CR 0xFD21A000
wdenke2211742002-11-02 23:30:20 +0000217
218/* bank 6 is unused */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200219/* PB6AP = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_EBC_PB6AP 0x00000000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200221/* PB6CR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_EBC_PB6CR 0x00000000
wdenke2211742002-11-02 23:30:20 +0000223
224/* bank 7 is LED register */
225/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
wdenke2211742002-11-02 23:30:20 +0000227/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
wdenke2211742002-11-02 23:30:20 +0000229
230/*-----------------------------------------------------------------------
231 * Start addresses for the final memory configuration
232 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_SDRAM_BASE 0x00000000
236#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
237#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
238#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
239#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000240
241/*
242 * For booting Linux, the board info and command line data
243 * have to be in the first 8 MB of memory, since this is
244 * the maximum mapped by the Linux kernel during initialization.
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000247/*-----------------------------------------------------------------------
248 * FLASH organization
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
251#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
wdenke2211742002-11-02 23:30:20 +0000252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
254#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
255#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
wdenke2211742002-11-02 23:30:20 +0000256
257#if 1 /* Use NVRAM for environment variables */
258/*-----------------------------------------------------------------------
259 * NVRAM organization
260 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200261#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
263#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200264#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
265/*define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
267#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
wdenke2211742002-11-02 23:30:20 +0000268
269#else /* Use Boot Flash for environment variables */
270/*-----------------------------------------------------------------------
271 * Flash EEPROM for environment
272 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200273#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200274#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
275#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
wdenke2211742002-11-02 23:30:20 +0000276
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200277#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
wdenke2211742002-11-02 23:30:20 +0000278#endif
279
280/*-----------------------------------------------------------------------
281 * I2C EEPROM (CAT24WC08) for environment
282 */
283#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200284#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
286#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenke2211742002-11-02 23:30:20 +0000287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
289#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenke2211742002-11-02 23:30:20 +0000290/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
292#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenke2211742002-11-02 23:30:20 +0000293 /* 16 byte page write mode using*/
294 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_I2C_MULTI_EEPROMS
wdenke2211742002-11-02 23:30:20 +0000296/*-----------------------------------------------------------------------
297 * Definitions for Serial Presence Detect EEPROM address
298 * (to get SDRAM settings)
299 */
300#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
301
wdenke2211742002-11-02 23:30:20 +0000302/*
303 * Init Memory Controller:
304 */
305#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
306#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
307
308/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
310#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenke2211742002-11-02 23:30:20 +0000311
312/*-----------------------------------------------------------------------
313 * Definitions for initial stack pointer and data area (in RAM)
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
316#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
317#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
318#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
319#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000320
Jon Loeligera5562902007-07-08 15:31:57 -0500321#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000322#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
323#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
324#endif
325
326/*
327 * FPGA(s) configuration
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
wdenke2211742002-11-02 23:30:20 +0000330#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */
331#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
332#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
333#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
334
335#endif /* __CONFIG_H */