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Reinhard Arltc2e49f72009-07-25 06:19:12 +02001/*
2 * esd vme8349 U-Boot configuration file
3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
4 *
Wolfgang Denk2ae18242010-10-06 09:05:45 +02005 * (C) Copyright 2006-2010
Reinhard Arltc2e49f72009-07-25 06:19:12 +02006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * reinhard.arlt@esd-electronics.de
9 * Based on the MPC8349EMDS config.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * vme8349 board configuration file.
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010038 * Top level Makefile configuration choices
39 */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#ifdef CONFIG_CADDY2
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010041#define VME_CADDY2
42#endif
43
44/*
Reinhard Arltc2e49f72009-07-25 06:19:12 +020045 * High Level Configuration Options
46 */
47#define CONFIG_E300 1 /* E300 Family */
48#define CONFIG_MPC83xx 1 /* MPC83xx family */
49#define CONFIG_MPC834x 1 /* MPC834x family */
50#define CONFIG_MPC8349 1 /* MPC8349 specific */
51#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
52
Wolfgang Denk2ae18242010-10-06 09:05:45 +020053#define CONFIG_SYS_TEXT_BASE 0xFFF00000
54
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010055#define CONFIG_MISC_INIT_R
56
Reinhard Arltc2e49f72009-07-25 06:19:12 +020057#define CONFIG_PCI
58/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
59#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
60
Wolfgang Denk2ae18242010-10-06 09:05:45 +020061#define CONFIG_PCI_66M
62#ifdef CONFIG_PCI_66M
Reinhard Arltc2e49f72009-07-25 06:19:12 +020063#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
64#else
65#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
66#endif
67
68#ifndef CONFIG_SYS_CLK_FREQ
Wolfgang Denk2ae18242010-10-06 09:05:45 +020069#ifdef CONFIG_PCI_66M
Reinhard Arltc2e49f72009-07-25 06:19:12 +020070#define CONFIG_SYS_CLK_FREQ 66000000
71#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
72#else
73#define CONFIG_SYS_CLK_FREQ 33000000
74#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
75#endif
76#endif
77
78#define CONFIG_SYS_IMMR 0xE0000000
79
80#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
81#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
82#define CONFIG_SYS_MEMTEST_END 0x00100000
83
84/*
85 * DDR Setup
86 */
87#define CONFIG_DDR_ECC /* only for ECC DDR module */
88#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +010089#define CONFIG_SPD_EEPROM
90#define SPD_EEPROM_ADDRESS 0x54
91#define CONFIG_SYS_READ_SPD vme8349_read_spd
Reinhard Arltc2e49f72009-07-25 06:19:12 +020092#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
93
94/*
95 * 32-bit data path mode.
96 *
97 * Please note that using this mode for devices with the real density of 64-bit
98 * effectively reduces the amount of available memory due to the effect of
99 * wrapping around while translating address to row/columns, for example in the
100 * 256MB module the upper 128MB get aliased with contents of the lower
101 * 128MB); normally this define should be used for devices with real 32-bit
102 * data path.
103 */
104#undef CONFIG_DDR_32BIT
105
106#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
107#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
108#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
109#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
110 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
111#define CONFIG_DDR_2T_TIMING
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100112#define CONFIG_SYS_DDRCDR 0x80080001
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200113
114/*
115 * FLASH on the Local Bus
116 */
117#define CONFIG_SYS_FLASH_CFI
118#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100119#ifdef VME_CADDY2
120#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
121#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200122#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
Kim Phillips4e7e12d2010-02-22 19:39:16 -0600123 (2 << BR_PS_SHIFT) | /* 16bit */ \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200124 BR_V) /* valid */
125
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100126#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200127#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100128#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */
129#else
130#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
131#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
132#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
Kim Phillips4e7e12d2010-02-22 19:39:16 -0600133 (2 << BR_PS_SHIFT) | /* 16bit */ \
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100134 BR_V) /* valid */
135
136#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */
137#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
138#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */
139#endif
140/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200141
142#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100143#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200144#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100145#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200146
147#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
148#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
149
150#undef CONFIG_SYS_FLASH_CHECKSUM
151#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
152#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
153
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200154#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200155
156#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
157#define CONFIG_SYS_RAMBOOT
158#else
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100159#undef CONFIG_SYS_RAMBOOT
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200160#endif
161
162#define CONFIG_SYS_INIT_RAM_LOCK 1
163#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
164#define CONFIG_SYS_INIT_RAM_END 0x1000 /* size */
165
166#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* size init data */
167#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
168 CONFIG_SYS_GBL_DATA_SIZE)
169#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
170
171#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
172#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Malloc size */
173
174/*
175 * Local Bus LCRR and LBCR regs
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100176 * LCRR: no DLL bypass, Clock divider is 4
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200177 * External Local Bus rate is
178 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
179 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500180#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200181#define CONFIG_SYS_LBC_LBCR 0x00000000
182
183#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
184
185/*
186 * Serial Port
187 */
188#define CONFIG_CONS_INDEX 1
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200189#define CONFIG_SYS_NS16550
190#define CONFIG_SYS_NS16550_SERIAL
191#define CONFIG_SYS_NS16550_REG_SIZE 1
192#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
193
194#define CONFIG_SYS_BAUDRATE_TABLE \
195 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
196
197#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
198#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
199
200#define CONFIG_CMDLINE_EDITING /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500201#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200202/* Use the HUSH parser */
203#define CONFIG_SYS_HUSH_PARSER
204#ifdef CONFIG_SYS_HUSH_PARSER
205#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
206#endif
207
208/* pass open firmware flat tree */
209#define CONFIG_OF_LIBFDT
210#define CONFIG_OF_BOARD_SETUP
211#define CONFIG_OF_STDOUT_VIA_ALIAS
212
213/* I2C */
214#define CONFIG_I2C_MULTI_BUS
215#define CONFIG_HARD_I2C /* I2C with hardware support*/
216#undef CONFIG_SOFT_I2C /* I2C bit-banged */
217#define CONFIG_FSL_I2C
218#define CONFIG_I2C_CMD_TREE
219#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
220#define CONFIG_SYS_I2C_SLAVE 0x7F
221#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */
222#define CONFIG_SYS_I2C1_OFFSET 0x3000
223#define CONFIG_SYS_I2C2_OFFSET 0x3100
224#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
Paul Gortmakerefaf6f12009-10-02 18:54:20 -0400225/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200226
227#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
228
229/* TSEC */
230#define CONFIG_SYS_TSEC1_OFFSET 0x24000
231#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
232#define CONFIG_SYS_TSEC2_OFFSET 0x25000
233#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
234
235/*
236 * General PCI
237 * Addresses are mapped 1-1.
238 */
239#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
240#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
241#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
242#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
243#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
244#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
245#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
246#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
247#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
248
249#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
250#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
251#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
252#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
253#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
254#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
255#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
256#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
257#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
258
259#if defined(CONFIG_PCI)
260
261#define PCI_64BIT
262#define PCI_ONE_PCI1
263#if defined(PCI_64BIT)
264#undef PCI_ALL_PCI1
265#undef PCI_TWO_PCI1
266#undef PCI_ONE_PCI1
267#endif
268
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100269#ifndef VME_CADDY2
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200270#define CONFIG_NET_MULTI
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100271#endif
272#define CONFIG_PCI_PNP /* do pci plug-and-play */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200273
274#undef CONFIG_EEPRO100
275#undef CONFIG_TULIP
276
277#if !defined(CONFIG_PCI_PNP)
278 #define PCI_ENET0_IOADDR 0xFIXME
279 #define PCI_ENET0_MEMADDR 0xFIXME
280 #define PCI_IDSEL_NUMBER 0xFIXME
281#endif
282
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100283#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
284#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
285
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200286#endif /* CONFIG_PCI */
287
288/*
289 * TSEC configuration
290 */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100291#ifdef VME_CADDY2
292#define CONFIG_E1000
293#else
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200294#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100295#endif
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200296
297#if defined(CONFIG_TSEC_ENET)
298#ifndef CONFIG_NET_MULTI
299#define CONFIG_NET_MULTI
300#endif
301
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100302#define CONFIG_GMII /* MII PHY management */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200303#define CONFIG_TSEC1
304#define CONFIG_TSEC1_NAME "TSEC0"
305#define CONFIG_TSEC2
306#define CONFIG_TSEC2_NAME "TSEC1"
307#define CONFIG_PHY_M88E1111
308#define TSEC1_PHY_ADDR 0x08
309#define TSEC2_PHY_ADDR 0x10
310#define TSEC1_PHYIDX 0
311#define TSEC2_PHYIDX 0
312#define TSEC1_FLAGS TSEC_GIGABIT
313#define TSEC2_FLAGS TSEC_GIGABIT
314
315/* Options are: TSEC[0-1] */
316#define CONFIG_ETHPRIME "TSEC0"
317
318#endif /* CONFIG_TSEC_ENET */
319
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100320#if defined(CONFIG_E1000)
321#ifndef CONFIG_NET_MULTI
322#define CONFIG_NET_MULTI
323#endif
324#endif
325
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200326/*
327 * Environment
328 */
329#ifndef CONFIG_SYS_RAMBOOT
330 #define CONFIG_ENV_IS_IN_FLASH
331 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
332 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
333 #define CONFIG_ENV_SIZE 0x2000
334
335/* Address and size of Redundant Environment Sector */
336#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
337#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
338
339#else
340 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
341 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
342 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
343 #define CONFIG_ENV_SIZE 0x2000
344#endif
345
346#define CONFIG_LOADS_ECHO /* echo on for serial download */
347#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
348
349/*
350 * BOOTP options
351 */
352#define CONFIG_BOOTP_BOOTFILESIZE
353#define CONFIG_BOOTP_BOOTPATH
354#define CONFIG_BOOTP_GATEWAY
355#define CONFIG_BOOTP_HOSTNAME
356
357/*
358 * Command line configuration.
359 */
360#include <config_cmd_default.h>
361
362#define CONFIG_CMD_I2C
363#define CONFIG_CMD_MII
364#define CONFIG_CMD_PING
365#define CONFIG_CMD_DATE
366#define CONFIG_SYS_RTC_BUS_NUM 0x01
367#define CONFIG_SYS_I2C_RTC_ADDR 0x32
368#define CONFIG_RTC_RX8025
369#define CONFIG_CMD_TSI148
370
371#if defined(CONFIG_PCI)
372 #define CONFIG_CMD_PCI
373#endif
374
375#if defined(CONFIG_SYS_RAMBOOT)
376 #undef CONFIG_CMD_ENV
377 #undef CONFIG_CMD_LOADS
378#endif
379
380#define CONFIG_CMD_ELF
381/* Pass Ethernet MAC to VxWorks */
382#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
383
384#undef CONFIG_WATCHDOG /* watchdog disabled */
385
386/*
387 * Miscellaneous configurable options
388 */
389#define CONFIG_SYS_LONGHELP /* undef to save memory */
390#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
391#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
392
393#if defined(CONFIG_CMD_KGDB)
394 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
395#else
396 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
397#endif
398
399#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
400#define CONFIG_SYS_MAXARGS 16 /* max num of command args */
401#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
402#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
403
404/*
405 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700406 * have to be in the first 256 MB of memory, since this is
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200407 * the maximum mapped by the Linux kernel during initialization.
408 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700409#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200410
411#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
412
413#define CONFIG_SYS_HRCW_LOW (\
414 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
415 HRCWL_DDR_TO_SCB_CLK_1X1 |\
416 HRCWL_CSB_TO_CLKIN |\
417 HRCWL_VCO_1X2 |\
418 HRCWL_CORE_TO_CSB_2X1)
419
420#if defined(PCI_64BIT)
421#define CONFIG_SYS_HRCW_HIGH (\
422 HRCWH_PCI_HOST |\
423 HRCWH_64_BIT_PCI |\
424 HRCWH_PCI1_ARBITER_ENABLE |\
425 HRCWH_PCI2_ARBITER_DISABLE |\
426 HRCWH_CORE_ENABLE |\
427 HRCWH_FROM_0X00000100 |\
428 HRCWH_BOOTSEQ_DISABLE |\
429 HRCWH_SW_WATCHDOG_DISABLE |\
430 HRCWH_ROM_LOC_LOCAL_16BIT |\
431 HRCWH_TSEC1M_IN_GMII |\
432 HRCWH_TSEC2M_IN_GMII)
433#else
434#define CONFIG_SYS_HRCW_HIGH (\
435 HRCWH_PCI_HOST |\
436 HRCWH_32_BIT_PCI |\
437 HRCWH_PCI1_ARBITER_ENABLE |\
438 HRCWH_PCI2_ARBITER_ENABLE |\
439 HRCWH_CORE_ENABLE |\
440 HRCWH_FROM_0X00000100 |\
441 HRCWH_BOOTSEQ_DISABLE |\
442 HRCWH_SW_WATCHDOG_DISABLE |\
443 HRCWH_ROM_LOC_LOCAL_16BIT |\
444 HRCWH_TSEC1M_IN_GMII |\
445 HRCWH_TSEC2M_IN_GMII)
446#endif
447
448/* System IO Config */
449#define CONFIG_SYS_SICRH 0
450#define CONFIG_SYS_SICRL SICRL_LDP_A
451
452#define CONFIG_SYS_HID0_INIT 0x000000000
Kim Phillips1a2e2032010-04-20 19:37:54 -0500453#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
454 HID0_ENABLE_INSTRUCTION_CACHE)
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200455
456#define CONFIG_SYS_HID2 HID2_HBE
457
458#define CONFIG_SYS_GPIO1_PRELIM
459#define CONFIG_SYS_GPIO1_DIR 0x00100000
460#define CONFIG_SYS_GPIO1_DAT 0x00100000
461
462#define CONFIG_SYS_GPIO2_PRELIM
463#define CONFIG_SYS_GPIO2_DIR 0x78900000
464#define CONFIG_SYS_GPIO2_DAT 0x70100000
465
466#define CONFIG_HIGH_BATS /* High BATs supported */
467
468/* DDR @ 0x00000000 */
469#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
470 BATL_MEMCOHERENCE)
471#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
472 BATU_VS | BATU_VP)
473
474/* PCI @ 0x80000000 */
475#ifdef CONFIG_PCI
476#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \
477 BATL_MEMCOHERENCE)
478#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
479 BATU_VS | BATU_VP)
480#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
481 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
482#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
483 BATU_VS | BATU_VP)
484#else
485#define CONFIG_SYS_IBAT1L (0)
486#define CONFIG_SYS_IBAT1U (0)
487#define CONFIG_SYS_IBAT2L (0)
488#define CONFIG_SYS_IBAT2U (0)
489#endif
490
491#ifdef CONFIG_MPC83XX_PCI2
492#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \
493 BATL_MEMCOHERENCE)
494#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
495 BATU_VS | BATU_VP)
496#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \
497 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
498#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
499 BATU_VS | BATU_VP)
500#else
501#define CONFIG_SYS_IBAT3L (0)
502#define CONFIG_SYS_IBAT3U (0)
503#define CONFIG_SYS_IBAT4L (0)
504#define CONFIG_SYS_IBAT4U (0)
505#endif
506
507/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
508#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
509 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
510#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
511 BATU_VS | BATU_VP)
512
513#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
514#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
515
516#if (CONFIG_SYS_DDR_SIZE == 512)
517#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
518 BATL_PP_10 | BATL_MEMCOHERENCE)
519#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
520 BATU_BL_256M | BATU_VS | BATU_VP)
521#else
522#define CONFIG_SYS_IBAT7L (0)
523#define CONFIG_SYS_IBAT7U (0)
524#endif
525
526#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
527#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
528#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
529#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
530#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
531#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
532#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
533#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
534#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
535#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
536#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
537#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
538#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
539#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
540#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
541#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
542
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200543#if defined(CONFIG_CMD_KGDB)
544#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
545#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
546#endif
547
548/*
549 * Environment Configuration
550 */
551#define CONFIG_ENV_OVERWRITE
552
553#if defined(CONFIG_TSEC_ENET)
554#define CONFIG_HAS_ETH0
555#define CONFIG_HAS_ETH1
556#endif
557
558#define CONFIG_HOSTNAME VME8349
559#define CONFIG_ROOTPATH /tftpboot/rootfs
560#define CONFIG_BOOTFILE uImage
561
Kim Phillips79f516b2009-08-21 16:34:38 -0500562#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200563
564#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
565#undef CONFIG_BOOTARGS /* boot command will set bootargs */
566
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100567#define CONFIG_BAUDRATE 9600
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200568
569#define CONFIG_EXTRA_ENV_SETTINGS \
570 "netdev=eth0\0" \
571 "hostname=vme8349\0" \
572 "nfsargs=setenv bootargs root=/dev/nfs rw " \
573 "nfsroot=${serverip}:${rootpath}\0" \
574 "ramargs=setenv bootargs root=/dev/ram rw\0" \
575 "addip=setenv bootargs ${bootargs} " \
576 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
577 ":${hostname}:${netdev}:off panic=1\0" \
578 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
579 "flash_nfs=run nfsargs addip addtty;" \
580 "bootm ${kernel_addr}\0" \
581 "flash_self=run ramargs addip addtty;" \
582 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
583 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
584 "bootm\0" \
585 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
586 "update=protect off fff00000 fff3ffff; " \
587 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
588 "upd=run load update\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500589 "fdtaddr=780000\0" \
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200590 "fdtfile=vme8349.dtb\0" \
591 ""
592
593#define CONFIG_NFSBOOTCOMMAND \
594 "setenv bootargs root=/dev/nfs rw " \
595 "nfsroot=$serverip:$rootpath " \
596 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
597 "console=$consoledev,$baudrate $othbootargs;" \
598 "tftp $loadaddr $bootfile;" \
599 "tftp $fdtaddr $fdtfile;" \
600 "bootm $loadaddr - $fdtaddr"
601
602#define CONFIG_RAMBOOTCOMMAND \
603 "setenv bootargs root=/dev/ram rw " \
604 "console=$consoledev,$baudrate $othbootargs;" \
605 "tftp $ramdiskaddr $ramdiskfile;" \
606 "tftp $loadaddr $bootfile;" \
607 "tftp $fdtaddr $fdtfile;" \
608 "bootm $loadaddr $ramdiskaddr $fdtaddr"
609
610#define CONFIG_BOOTCOMMAND "run flash_self"
611
Reinhard Arlt1dee9be2009-12-08 09:13:08 +0100612#ifndef __ASSEMBLY__
613int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
614 unsigned char *buffer, int len);
615#endif
616
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200617#endif /* __CONFIG_H */