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wdenk96e48cf2003-08-05 18:22:44 +00001/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26#if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
27
28#include <asm/processor.h>
29#include <asm/io.h>
30#include <pci.h>
31#include <mpc5xxx.h>
32
33/* System RAM mapped over PCI */
34#define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
35#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
36#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
37
38/* PCIIWCR bit fields */
39#define IWCR_MEM (0 << 3)
40#define IWCR_IO (1 << 3)
41#define IWCR_READ (0 << 1)
42#define IWCR_READLINE (1 << 1)
43#define IWCR_READMULT (2 << 1)
44#define IWCR_EN (1 << 0)
45
46static int mpc5200_read_config_dword(struct pci_controller *hose,
47 pci_dev_t dev, int offset, u32* value)
48{
49 *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
50 eieio();
wdenk35656de2003-09-14 19:08:39 +000051 udelay(10);
wdenk96e48cf2003-08-05 18:22:44 +000052 *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
53 eieio();
54 *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
wdenk35656de2003-09-14 19:08:39 +000055 udelay(10);
wdenk96e48cf2003-08-05 18:22:44 +000056 return 0;
57}
58
59static int mpc5200_write_config_dword(struct pci_controller *hose,
60 pci_dev_t dev, int offset, u32 value)
61{
62 *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
63 eieio();
wdenk35656de2003-09-14 19:08:39 +000064 udelay(10);
wdenk96e48cf2003-08-05 18:22:44 +000065 out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
66 eieio();
67 *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
wdenk35656de2003-09-14 19:08:39 +000068 udelay(10);
wdenk96e48cf2003-08-05 18:22:44 +000069 return 0;
70}
71
72void pci_mpc5xxx_init (struct pci_controller *hose)
73{
74 hose->first_busno = 0;
75 hose->last_busno = 0xff;
76
77 /* System space */
78 pci_set_region(hose->regions + 0,
79 CONFIG_PCI_MEMORY_BUS,
80 CONFIG_PCI_MEMORY_PHYS,
81 CONFIG_PCI_MEMORY_SIZE,
82 PCI_REGION_MEM | PCI_REGION_MEMORY);
83
84 /* PCI memory space */
85 pci_set_region(hose->regions + 1,
86 CONFIG_PCI_MEM_BUS,
87 CONFIG_PCI_MEM_PHYS,
88 CONFIG_PCI_MEM_SIZE,
89 PCI_REGION_MEM);
90
91 /* PCI IO space */
92 pci_set_region(hose->regions + 2,
93 CONFIG_PCI_IO_BUS,
94 CONFIG_PCI_IO_PHYS,
95 CONFIG_PCI_IO_SIZE,
96 PCI_REGION_IO);
97
98 hose->region_count = 3;
99
100 pci_register_hose(hose);
101
102 /* GPIO Multiplexing - enable PCI */
103 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
wdenk42d1f032003-10-15 23:53:47 +0000104
wdenk96e48cf2003-08-05 18:22:44 +0000105 /* Set host bridge as pci master and enable memory decoding */
106 *(vu_long *)MPC5XXX_PCI_CMD |=
107 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
wdenk42d1f032003-10-15 23:53:47 +0000108
wdenk96e48cf2003-08-05 18:22:44 +0000109 /* Set maximum latency timer */
110 *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
111
112 /* Set cache line size */
113 *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
114 (CFG_CACHELINE_SIZE / 4);
wdenk42d1f032003-10-15 23:53:47 +0000115
wdenk96e48cf2003-08-05 18:22:44 +0000116 /* Map MBAR to PCI space */
117 *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
wdenk3c74e322004-02-22 23:46:08 +0000118 *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1;
wdenk42d1f032003-10-15 23:53:47 +0000119
wdenk96e48cf2003-08-05 18:22:44 +0000120 /* Map RAM to PCI space */
121 *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
122 *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
123
124 /* Enable snooping for RAM */
125 *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
126 *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
127
128 /* Park XLB on PCI */
129 *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
130 *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
131
wdenk373e6be2003-09-16 17:20:34 +0000132#if 0
wdenk96e48cf2003-08-05 18:22:44 +0000133 /* Enable piplining */
134 *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
wdenk373e6be2003-09-16 17:20:34 +0000135#endif
wdenk42d1f032003-10-15 23:53:47 +0000136
wdenk96e48cf2003-08-05 18:22:44 +0000137 /* Disable interrupts from PCI controller */
138 *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
139 *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
wdenk42d1f032003-10-15 23:53:47 +0000140
wdenk96e48cf2003-08-05 18:22:44 +0000141 /* Disable initiator windows */
142 *(vu_long *)MPC5XXX_PCI_IWCR = 0;
wdenk42d1f032003-10-15 23:53:47 +0000143
wdenk96e48cf2003-08-05 18:22:44 +0000144 /* Map PCI memory to physical space */
145 *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
146 (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
147 (CONFIG_PCI_MEM_BUS >> 16);
148 *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
149
150 /* Map PCI I/O to physical space */
151 *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
152 (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
153 (CONFIG_PCI_IO_BUS >> 16);
154 *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
155
156 /* Reset the PCI bus */
157 *(vu_long *)MPC5XXX_PCI_GSCR |= 1;
158 udelay(1000);
159 *(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
160 udelay(1000);
161
162 pci_set_ops(hose,
163 pci_hose_read_config_byte_via_dword,
164 pci_hose_read_config_word_via_dword,
165 mpc5200_read_config_dword,
166 pci_hose_write_config_byte_via_dword,
167 pci_hose_write_config_word_via_dword,
168 mpc5200_write_config_dword);
wdenk42d1f032003-10-15 23:53:47 +0000169
wdenk96e48cf2003-08-05 18:22:44 +0000170 udelay(1000);
171
172#ifdef CONFIG_PCI_SCAN_SHOW
173 printf("PCI: Bus Dev VenId DevId Class Int\n");
174#endif
175
176 hose->last_busno = pci_hose_scan(hose);
177}
178#endif /* CONFIG_PCI && CONFIG_MPC5200 */