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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 3d420cbd355a5f09e4f113eb10579a264a8ef138 / . / board / nvidia / jetson-tk1 / pinmux-config-jetson-tk1.h
blob: d338818a64eb898697db9ac014fb392fea858674 [file] [log] [blame]
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
8#define _PINMUX_CONFIG_JETSON_TK1_H_
9
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]10#define GPIO_INIT(_gpio, _init) \
11 { \
12 .gpio = GPIO_P##_gpio, \
13 .init = TEGRA_GPIO_INIT_##_init, \
14 }
15
16static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
17 /* gpio, init_val */
18 GPIO_INIT(C7, IN),
19 GPIO_INIT(G0, OUT0),
20 GPIO_INIT(G1, OUT0),
21 GPIO_INIT(G2, IN),
22 GPIO_INIT(G3, IN),
23 GPIO_INIT(H2, OUT0),
24 GPIO_INIT(H3, OUT0),
25 GPIO_INIT(H4, IN),
26 GPIO_INIT(H5, OUT0),
27 GPIO_INIT(H6, IN),
28 GPIO_INIT(H7, OUT0),
29 GPIO_INIT(I0, OUT0),
30 GPIO_INIT(I2, OUT0),
31 GPIO_INIT(I4, OUT0),
32 GPIO_INIT(I5, IN),
33 GPIO_INIT(I6, IN),
34 GPIO_INIT(J0, IN),
35 GPIO_INIT(J2, IN),
36 GPIO_INIT(K1, OUT0),
37 GPIO_INIT(K2, IN),
38 GPIO_INIT(K3, IN),
39 GPIO_INIT(K4, OUT0),
40 GPIO_INIT(K5, OUT0),
41 GPIO_INIT(K6, OUT0),
42 GPIO_INIT(N7, IN),
43 GPIO_INIT(O0, IN),
44 GPIO_INIT(O1, IN),
45 GPIO_INIT(O2, IN),
46 GPIO_INIT(O3, IN),
47 GPIO_INIT(O4, IN),
48 GPIO_INIT(O5, IN),
49 GPIO_INIT(O6, OUT0),
50 GPIO_INIT(O7, IN),
51 GPIO_INIT(P0, OUT0),
52 GPIO_INIT(P1, OUT0),
53 GPIO_INIT(P2, OUT0),
54 GPIO_INIT(Q0, IN),
55 GPIO_INIT(Q1, IN),
56 GPIO_INIT(Q2, IN),
57 GPIO_INIT(Q5, IN),
58 GPIO_INIT(Q6, IN),
59 GPIO_INIT(Q7, IN),
60 GPIO_INIT(R0, OUT0),
61 GPIO_INIT(R1, OUT0),
62 GPIO_INIT(R2, OUT0),
63 GPIO_INIT(R4, IN),
64 GPIO_INIT(R5, OUT0),
65 GPIO_INIT(R7, IN),
66 GPIO_INIT(S0, IN),
67 GPIO_INIT(S3, OUT0),
68 GPIO_INIT(S4, OUT0),
69 GPIO_INIT(S5, IN),
70 GPIO_INIT(S6, OUT0),
71 GPIO_INIT(T0, OUT0),
72 GPIO_INIT(T1, OUT0),
73 GPIO_INIT(U0, OUT0),
74 GPIO_INIT(U1, IN),
75 GPIO_INIT(U2, IN),
76 GPIO_INIT(U3, OUT0),
77 GPIO_INIT(U4, OUT0),
78 GPIO_INIT(U5, IN),
79 GPIO_INIT(U6, IN),
80 GPIO_INIT(V0, IN),
81 GPIO_INIT(V1, IN),
82 GPIO_INIT(W2, IN),
83 GPIO_INIT(W3, IN),
84 GPIO_INIT(X1, OUT0),
85 GPIO_INIT(X3, IN),
86 GPIO_INIT(X4, OUT0),
87 GPIO_INIT(X5, IN),
88 GPIO_INIT(X6, IN),
89 GPIO_INIT(X7, OUT0),
90 GPIO_INIT(BB3, OUT0),
91 GPIO_INIT(BB5, OUT0),
92 GPIO_INIT(BB6, OUT0),
93 GPIO_INIT(BB7, OUT0),
94 GPIO_INIT(CC1, IN),
95 GPIO_INIT(CC2, IN),
96 GPIO_INIT(CC5, OUT0),
97 GPIO_INIT(EE1, OUT0),
98 GPIO_INIT(FF1, OUT0),
99 GPIO_INIT(FF2, IN),
100};
101
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]102#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
103 { \
104 .pingrp = PMUX_PINGRP_##_pingrp, \
105 .func = PMUX_FUNC_##_mux, \
106 .pull = PMUX_PULL_##_pull, \
107 .tristate = PMUX_TRI_##_tri, \
108 .io = PMUX_PIN_##_io, \
109 .od = PMUX_PIN_OD_##_od, \
110 .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
111 .lock = PMUX_PIN_LOCK_DEFAULT, \
112 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
113 }
114
115static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
116 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
117 PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
118 PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
119 PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
120 PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
121 PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
122 PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
123 PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
124 PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
125 PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
126 PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
127 PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
128 PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
129 PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
130 PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
131 PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
132 PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
133 PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
134 PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
135 PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]136 PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
137 PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
138 PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
139 PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
140 PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]141 PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
142 PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
143 PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
144 PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
145 PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
146 PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]147 PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
148 PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
149 PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
150 PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
151 PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
152 PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
153 PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]154 PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]155 PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]156 PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]157 PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
158 PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
159 PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]160 PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]161 PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
162 PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]163 PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
164 PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
165 PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
166 PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]167 PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
168 PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
169 PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
170 PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
171 PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
172 PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]173 PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
174 PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
175 PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
176 PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
177 PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
178 PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
179 PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]180 PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
181 PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
182 PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
183 PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
184 PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
185 PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
186 PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
187 PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
188 PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
189 PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
190 PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
191 PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]192 PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
193 PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
194 PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
195 PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
196 PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]197 PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
198 PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
199 PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]200 PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
201 PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]202 PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
203 PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
204 PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
205 PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
206 PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
207 PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]208 PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]209 PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
210 PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]211 PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]212 PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
213 PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]214 PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
215 PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]216 PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
217 PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
218 PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
219 PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]220 PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]221 PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
222 PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]223 PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
224 PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
225 PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]226 PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
227 PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
228 PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
229 PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
230 PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
231 PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
232 PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
233 PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
234 PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]235 PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
236 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
237 PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
238 PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]239 PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
240 PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]241 PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
242 PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
243 PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
244 PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
245 PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]246 PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]247 PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]248 PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
249 PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
250 PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
251 PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
252 PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]253 PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
254 PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
255 PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
256 PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
257 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
258 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
259 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
260 PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
261 PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
262 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
263 PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
264 PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
265 PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
266 PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
267 PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
268 PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
269 PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
270 PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
271 PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
272 PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
273 PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
274 PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
275 PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]276 PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]277 PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]278 PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
279 PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
280 PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]281 PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]282 PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
283 PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]284 PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]285 PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]286 PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]287 PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]288 PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
289 PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
290 PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
291 PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
292 PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]293 PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
294 PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]295 PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
296 PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
297 PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
298 PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
299 PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
300 PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
301 PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
302};
303
304#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
305 { \
306 .drvgrp = PMUX_DRVGRP_##_drvgrp, \
307 .slwf = _slwf, \
308 .slwr = _slwr, \
309 .drvup = _drvup, \
310 .drvdn = _drvdn, \
311 .lpmd = PMUX_LPMD_##_lpmd, \
312 .schmt = PMUX_SCHMT_##_schmt, \
313 .hsm = PMUX_HSM_##_hsm, \
314 }
315
316static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
317};
318
319#endif /* PINMUX_CONFIG_JETSON_TK1_H */