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Paul Gortmakerbd42bbb2009-09-18 19:08:46 -04001Intro:
2======
Joe Hamman9e3ed392007-12-13 06:45:14 -06003
Paul Gortmakerbd42bbb2009-09-18 19:08:46 -04004The SBC8548 is a stand alone single board computer with a 1GHz
5MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
6memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
7and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
8ethernet connections.
Joe Hamman9e3ed392007-12-13 06:45:14 -06009
Paul Gortmakerbd42bbb2009-09-18 19:08:46 -040010U-boot Configuration:
11=====================
Joe Hamman9e3ed392007-12-13 06:45:14 -060012
Paul Gortmakerbd42bbb2009-09-18 19:08:46 -040013The following possible u-boot configuration targets are available:
Joe Hamman9e3ed392007-12-13 06:45:14 -060014
Paul Gortmakerbd42bbb2009-09-18 19:08:46 -040015 1) sbc8548_config
16 2) sbc8548_PCI_33_config
17 3) sbc8548_PCI_66_config
18 4) sbc8548_PCI_33_PCIE_config
19 5) sbc8548_PCI_66_PCIE_config
20
21Generally speaking, most people should choose to use #5. Details
22of each choice are listed below.
23
24Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
25will be left empty (M66EN high), and so the board will operate with
26a base clock of 66MHz. Note that you need both PCI enabled in u-boot
27and linux in order to have functional PCI under linux.
28
29The second enables PCI support and builds for a 33MHz clock rate. Note
30that if a 33MHz 32bit card is inserted in the slot, then the whole board
31will clock down to a 33MHz base clock instead of the default 66MHz. This
32will change the baud clocks and mess up your serial console output if you
33were previously running at 66MHz. If you want to use a 33MHz PCI card,
34then you should build a U-Boot with a _PCI_33_ config and store this
35to flash prior to powering down the board and inserting the 33MHz PCI
36card. [The above discussion assumes that the SW2[1-4] has not been changed
37to reflect a different CCB:SYSCLK ratio]
38
39The third option builds PCI support in, and leaves the clocking at the
40default 66MHz. Options four and five are just repeats of option two
41and three, but with PCI-e support enabled as well.
42
43PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
44is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
45a 33MHz PCI configuration is currently untested.)
46
47 => pci 0
48 Scanning PCI devices on bus 0
49 BusDevFun VendorId DeviceId Device Class Sub-Class
50 _____________________________________________________________
51 00.00.00 0x1057 0x0012 Processor 0x20
52 00.01.00 0x8086 0x1026 Network controller 0x00
53 => pci 1
54 Scanning PCI devices on bus 1
55 BusDevFun VendorId DeviceId Device Class Sub-Class
56 _____________________________________________________________
57 01.00.00 0x1957 0x0012 Processor 0x20
58 => pci 2
59 Scanning PCI devices on bus 2
60 BusDevFun VendorId DeviceId Device Class Sub-Class
61 _____________________________________________________________
62 02.00.00 0x1148 0x9e00 Network controller 0x00
63 =>
Joe Hamman9e3ed392007-12-13 06:45:14 -060064
65
Paul Gortmakerdd9ca982009-09-25 11:14:11 -040066Updating U-boot with U-boot:
67============================
68
69Note that versions of u-boot up to and including 2009.08 had u-boot stored
70at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
710xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
72update u-boot with u-boot and it uses the old address, you will render
73your board inoperable, and you will require JTAG recovery.
74
75The following steps list how to update with the current address:
76
77 tftp u-boot.bin
78 md 200000 10
79 protect off all
80 erase fffa0000 ffffffff
81 cp.b 200000 fffa0000 60000
82 md fffa0000 10
83 protect on all
84
85The "md" steps in the above are just a precautionary step that allow
86you to confirm the u-boot version that was downloaded, and then confirm
87that it was copied to flash.
88
89
Paul Gortmakerbd42bbb2009-09-18 19:08:46 -040090Hardware Reference:
91===================
Joe Hamman9e3ed392007-12-13 06:45:14 -060092
Paul Gortmakerbd42bbb2009-09-18 19:08:46 -040093The following contains some summary information on hardware settings
94that are relevant to u-boot, based on the board manual. For the
95most up to date and complete details of the board, please request the
96reference manual ERG-00327-001.pdf from www.windriver.com
97
98Boot flash:
99 intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
100
101Sodimm flash:
102 intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
103
104
105 Jumpers:
106
107Jumper Name ON OFF
108----------------------------------------------------------------
109JP12 CS0/CS6 swap see note[*] see note[*]
110
111JP13 SODIMM flash write OK writes disabled
112 write prot.
113
114JP14 HRESET/TRST joined isolated
115
116JP15 PWR ON when AC pwr use S1 for on/off
117
118JP16 Demo LEDs lit not lit
119
120JP19 PCI mode PCI PCI-X
121
122
123[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
124onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
125is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
126SODIMM flash and /CS6 is for the boot flash. Note that in this
127alternate setting, you also need to switch SW2.8 to ON. Currently
128u-boot doesn't support booting off the SODIMM in this alternate
129setting without manually altering BR0/OR0 and BR6/OR6 in the
130board config file appropriately.
131
132
133 Switches:
134
135The defaults are marked with a *
136
137Name Desc. ON OFF
138------------------------------------------------------------------
139S1 Pwr toggle n/a n/a
140
141SW2.1 CFG_SYS_PLL0 1 0*
142SW2.2 CFG_SYS_PLL1 1* 0
143SW2.3 CFG_SYS_PLL2 1* 0
144SW2.4 CFG_SYS_PLL3 1 0*
145SW2.5 CFG_CORE_PLL0 1* 0
146SW2.6 CFG_CORE_PLL1 1 0*
147SW2.7 CFG_CORE_PLL2 1* 0
148SW2.8 CFG_ROM_LOC1 1 0*
149
150SW3.1 CFG_HOST_AGT0 1* 0
151SW3.2 CFG_HOST_AGT1 1* 0
152SW3.3 CFG_HOST_AGT2 1* 0
153SW3.4 CFG_IO_PORTS0 1* 0
154SW3.5 CFG_IO_PORTS0 1 0*
155SW3.6 CFG_IO_PORTS0 1 0*
156
157SerDes CLK(MHz) SW5.1 SW5.2
158----------------------------------------------
15925 0 0
160100* 1 0
161125 0 1
162200 1 1
163
164SerDes CLK spread SW5.3 SW5.4
165----------------------------------------------
166+/- 0.25% 0 0
167-0.50% 1 0
168-0.75% 0 1
169No Spread* 1 1
170
171SW4 settings are readable from the EPLD and are currently not used for
172any hardware settings (i.e. user configuration switches).
173
174 LEDs:
175
176Name Desc. ON OFF
177------------------------------------------------------------------
178D13 PCI/PCI-X PCI-X PCI
179D14 3.3V PWR 3.3V no power
180D15 SYSCLK 66MHz 33MHz
181
182
183 Default Memory Map:
184
185start end CS<n> width Desc.
186----------------------------------------------------------------------
1870000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
188f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
189f800_0000 f8b0_1fff CS5 - EPLD
190fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB)
191ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
192
193The EPLD on CS5 demuxes the following devices at the following offsets:
194
195offset size width device
196--------------------------------------------------------
1970 1fff 8 7 segment display LED
19810_0000 1fff 4 user switches
19930_0000 1fff 4 HW Rev. register
200b0_0000 1fff 8 8kB EEPROM