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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 3d83c4a1d4dd7ea230d5b5c073e503dca883e409 / . / drivers / clk / sunxi / clk_a31.c
blob: fa6e3eeef0e2f5b15e6da953147f44e5ae98761c [file] [log] [blame]
Jagan Teki4927e2e2018-08-02 23:15:34 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions B.V.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun6i-a31-ccu.h>
13#include <dt-bindings/reset/sun6i-a31-ccu.h>
14
15static struct ccu_clk_gate a31_gates[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]20 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
23 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
Jagan Teki4927e2e2018-08-02 23:15:34 +0530[diff] [blame]24 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
25 [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)),
26 [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)),
27 [CLK_AHB1_OHCI0] = GATE(0x060, BIT(29)),
28 [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
29 [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
30
Jagan Teki4acc7112018-12-30 21:29:24 +0530[diff] [blame]31 [CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
32 [CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
33 [CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
34 [CLK_APB2_UART3] = GATE(0x06c, BIT(19)),
35 [CLK_APB2_UART4] = GATE(0x06c, BIT(20)),
36 [CLK_APB2_UART5] = GATE(0x06c, BIT(21)),
37
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]38 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
39 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
40 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
41 [CLK_SPI3] = GATE(0x0ac, BIT(31)),
42
Jagan Teki4927e2e2018-08-02 23:15:34 +0530[diff] [blame]43 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
44 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
45 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
46 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
47 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
48 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
49};
50
51static struct ccu_reset a31_resets[] = {
52 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
53 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
54 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
55
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]56 [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
57 [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
58 [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
59 [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]60 [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
61 [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
62 [RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)),
63 [RST_AHB1_SPI3] = RESET(0x2c0, BIT(23)),
Jagan Teki4927e2e2018-08-02 23:15:34 +0530[diff] [blame]64 [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)),
65 [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)),
66 [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)),
67 [RST_AHB1_OHCI0] = RESET(0x2c0, BIT(29)),
68 [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
69 [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
Jagan Teki8606f962018-12-30 21:37:31 +0530[diff] [blame]70
71 [RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
72 [RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
73 [RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
74 [RST_APB2_UART3] = RESET(0x2d8, BIT(19)),
75 [RST_APB2_UART4] = RESET(0x2d8, BIT(20)),
76 [RST_APB2_UART5] = RESET(0x2d8, BIT(21)),
Jagan Teki4927e2e2018-08-02 23:15:34 +0530[diff] [blame]77};
78
79static const struct ccu_desc a31_ccu_desc = {
80 .gates = a31_gates,
81 .resets = a31_resets,
82};
83
84static int a31_clk_bind(struct udevice *dev)
85{
86 return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
87}
88
89static const struct udevice_id a31_clk_ids[] = {
90 { .compatible = "allwinner,sun6i-a31-ccu",
91 .data = (ulong)&a31_ccu_desc },
92 { }
93};
94
95U_BOOT_DRIVER(clk_sun6i_a31) = {
96 .name = "sun6i_a31_ccu",
97 .id = UCLASS_CLK,
98 .of_match = a31_clk_ids,
99 .priv_auto_alloc_size = sizeof(struct ccu_priv),
100 .ops = &sunxi_clk_ops,
101 .probe = sunxi_clk_probe,
102 .bind = a31_clk_bind,
103};