| Mario Six | 76fdad1 | 2018-08-06 10:23:35 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * (C) Copyright 2018 |
| 4 | * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc |
| 5 | */ |
| 6 | |
| 7 | #ifndef _SYSRESET_MPC83XX_H_ |
| 8 | #define _SYSRESET_MPC83XX_H_ |
| 9 | |
| 10 | /* |
| 11 | * String array for all possible event types; indexed by the EVENT field of the |
| 12 | * AEATR register. |
| 13 | */ |
| 14 | static const char * const event[] = { |
| 15 | "Address Time Out", |
| 16 | "Data Time Out", |
| 17 | "Address Only Transfer Type", |
| 18 | "External Control Word Transfer Type", |
| 19 | "Reserved Transfer Type", |
| 20 | "Transfer Error", |
| 21 | "reserved", |
| 22 | "reserved" |
| 23 | }; |
| 24 | |
| 25 | /* |
| 26 | * String array for all possible master IDs, which reflects the source of the |
| 27 | * transaction that caused the error; indexed by the MSTR_ID field of the AEATR |
| 28 | * register. |
| 29 | */ |
| 30 | static const char * const master[] = { |
| 31 | "e300 Core Data Transaction", |
| 32 | "reserved", |
| 33 | "e300 Core Instruction Fetch", |
| 34 | "reserved", |
| 35 | "TSEC1", |
| 36 | "TSEC2", |
| 37 | "USB MPH", |
| 38 | "USB DR", |
| 39 | "Encryption Core", |
| 40 | "I2C Boot Sequencer", |
| 41 | "JTAG", |
| 42 | "reserved", |
| 43 | "eSDHC", |
| 44 | "PCI1", |
| 45 | "PCI2", |
| 46 | "DMA", |
| 47 | "QUICC Engine 00", |
| 48 | "QUICC Engine 01", |
| 49 | "QUICC Engine 10", |
| 50 | "QUICC Engine 11", |
| 51 | "reserved", |
| 52 | "reserved", |
| 53 | "reserved", |
| 54 | "reserved", |
| 55 | "SATA1", |
| 56 | "SATA2", |
| 57 | "SATA3", |
| 58 | "SATA4", |
| 59 | "reserved", |
| 60 | "PCI Express 1", |
| 61 | "PCI Express 2", |
| 62 | "TDM-DMAC" |
| 63 | }; |
| 64 | |
| 65 | /* |
| 66 | * String array for all possible transfer types; indexed by the TTYPE field of |
| 67 | * the AEATR register. |
| 68 | */ |
| 69 | static const char * const transfer[] = { |
| 70 | "Address-only, Clean Block", |
| 71 | "Address-only, lwarx reservation set", |
| 72 | "Single-beat or Burst write", |
| 73 | "reserved", |
| 74 | "Address-only, Flush Block", |
| 75 | "reserved", |
| 76 | "Burst write", |
| 77 | "reserved", |
| 78 | "Address-only, sync", |
| 79 | "Address-only, tlbsync", |
| 80 | "Single-beat or Burst read", |
| 81 | "Single-beat or Burst read", |
| 82 | "Address-only, Kill Block", |
| 83 | "Address-only, icbi", |
| 84 | "Burst read", |
| 85 | "reserved", |
| 86 | "Address-only, eieio", |
| 87 | "reserved", |
| 88 | "Single-beat write", |
| 89 | "reserved", |
| 90 | "ecowx - Illegal single-beat write", |
| 91 | "reserved", |
| 92 | "reserved", |
| 93 | "reserved", |
| 94 | "Address-only, TLB Invalidate", |
| 95 | "reserved", |
| 96 | "Single-beat or Burst read", |
| 97 | "reserved", |
| 98 | "eciwx - Illegal single-beat read", |
| 99 | "reserved", |
| 100 | "Burst read", |
| 101 | "reserved" |
| 102 | }; |
| 103 | #endif /* _SYSRESET_MPC83XX_H_ */ |