blob: fe1fb85131e33f545412418e1ccb2a87297a010e [file] [log] [blame]
Simon Glass1ff4f322016-01-18 20:19:18 -07001/*
2 * Copyright (C) 2014 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <pch.h>
10
11#define BIOS_CTRL 0xd8
12
Bin Meng3e389d82016-02-01 01:40:42 -080013static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
Simon Glass1ff4f322016-01-18 20:19:18 -070014{
15 u32 rcba;
16
17 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
18 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
19 rcba = rcba & 0xffffc000;
20 *sbasep = rcba + 0x3020;
21
22 return 0;
23}
24
Simon Glass1ff4f322016-01-18 20:19:18 -070025static int pch7_set_spi_protect(struct udevice *dev, bool protect)
26{
27 uint8_t bios_cntl;
28
29 /* Adjust the BIOS write protect to dis/allow write commands */
30 dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
31 if (protect)
32 bios_cntl &= ~BIOS_CTRL_BIOSWE;
33 else
34 bios_cntl |= BIOS_CTRL_BIOSWE;
35 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
36
37 return 0;
38}
39
40static const struct pch_ops pch7_ops = {
Bin Meng3e389d82016-02-01 01:40:42 -080041 .get_spi_base = pch7_get_spi_base,
Simon Glass1ff4f322016-01-18 20:19:18 -070042 .set_spi_protect = pch7_set_spi_protect,
43};
44
45static const struct udevice_id pch7_ids[] = {
46 { .compatible = "intel,pch7" },
47 { }
48};
49
50U_BOOT_DRIVER(pch7_drv) = {
51 .name = "intel-pch7",
52 .id = UCLASS_PCH,
53 .of_match = pch7_ids,
54 .ops = &pch7_ops,
55};