blob: 629b529a69550e832ffca1684a5b8c60a85109d1 [file] [log] [blame]
wdenk80885a92004-02-26 23:46:20 +00001/*
2 * URB OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * usb-ohci.h
8 */
9
10
11static int cc_to_error[16] = {
12
13/* mapping of the OHCI CC status to error codes */
14 /* No Error */ 0,
15 /* CRC Error */ USB_ST_CRC_ERR,
16 /* Bit Stuff */ USB_ST_BIT_ERR,
17 /* Data Togg */ USB_ST_CRC_ERR,
18 /* Stall */ USB_ST_STALLED,
19 /* DevNotResp */ -1,
20 /* PIDCheck */ USB_ST_BIT_ERR,
21 /* UnExpPID */ USB_ST_BIT_ERR,
22 /* DataOver */ USB_ST_BUF_ERR,
23 /* DataUnder */ USB_ST_BUF_ERR,
24 /* reservd */ -1,
25 /* reservd */ -1,
26 /* BufferOver */ USB_ST_BUF_ERR,
27 /* BuffUnder */ USB_ST_BUF_ERR,
28 /* Not Access */ -1,
29 /* Not Access */ -1
30};
31
32/* ED States */
33
34#define ED_NEW 0x00
35#define ED_UNLINK 0x01
36#define ED_OPER 0x02
37#define ED_DEL 0x04
38#define ED_URB_DEL 0x08
39
40/* usb_ohci_ed */
41struct ed {
42 __u32 hwINFO;
43 __u32 hwTailP;
44 __u32 hwHeadP;
45 __u32 hwNextED;
46
47 struct ed *ed_prev;
48 __u8 int_period;
49 __u8 int_branch;
50 __u8 int_load;
51 __u8 int_interval;
52 __u8 state;
53 __u8 type;
54 __u16 last_iso;
55 struct ed *ed_rm_list;
56
57 struct usb_device *usb_dev;
58 __u32 unused[3];
Peter Tyserf9a109b2009-04-20 11:08:46 -050059} __attribute__((aligned(16)));
wdenk80885a92004-02-26 23:46:20 +000060typedef struct ed ed_t;
61
62
63/* TD info field */
64#define TD_CC 0xf0000000
65#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
66#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
67#define TD_EC 0x0C000000
68#define TD_T 0x03000000
69#define TD_T_DATA0 0x02000000
70#define TD_T_DATA1 0x03000000
71#define TD_T_TOGGLE 0x00000000
72#define TD_R 0x00040000
73#define TD_DI 0x00E00000
74#define TD_DI_SET(X) (((X) & 0x07)<< 21)
75#define TD_DP 0x00180000
76#define TD_DP_SETUP 0x00000000
77#define TD_DP_IN 0x00100000
78#define TD_DP_OUT 0x00080000
79
80#define TD_ISO 0x00010000
81#define TD_DEL 0x00020000
82
83/* CC Codes */
84#define TD_CC_NOERROR 0x00
85#define TD_CC_CRC 0x01
86#define TD_CC_BITSTUFFING 0x02
87#define TD_CC_DATATOGGLEM 0x03
88#define TD_CC_STALL 0x04
89#define TD_DEVNOTRESP 0x05
90#define TD_PIDCHECKFAIL 0x06
91#define TD_UNEXPECTEDPID 0x07
92#define TD_DATAOVERRUN 0x08
93#define TD_DATAUNDERRUN 0x09
94#define TD_BUFFEROVERRUN 0x0C
95#define TD_BUFFERUNDERRUN 0x0D
96#define TD_NOTACCESSED 0x0F
97
98
99#define MAXPSW 1
100
101struct td {
102 __u32 hwINFO;
103 __u32 hwCBP; /* Current Buffer Pointer */
104 __u32 hwNextTD; /* Next TD Pointer */
105 __u32 hwBE; /* Memory Buffer End Pointer */
106
wdenk80885a92004-02-26 23:46:20 +0000107 __u8 unused;
108 __u8 index;
109 struct ed *ed;
110 struct td *next_dl_td;
111 struct usb_device *usb_dev;
112 int transfer_len;
113 __u32 data;
114
115 __u32 unused2[2];
Peter Tyserf9a109b2009-04-20 11:08:46 -0500116} __attribute__((aligned(32)));
wdenk80885a92004-02-26 23:46:20 +0000117typedef struct td td_t;
118
119#define OHCI_ED_SKIP (1 << 14)
120
121/*
122 * The HCCA (Host Controller Communications Area) is a 256 byte
123 * structure defined in the OHCI spec. that the host controller is
124 * told the base address of. It must be 256-byte aligned.
125 */
126
127#define NUM_INTS 32 /* part of the OHCI standard */
128struct ohci_hcca {
129 __u32 int_table[NUM_INTS]; /* Interrupt ED table */
wdenk80885a92004-02-26 23:46:20 +0000130 __u16 pad1; /* set to 0 on each frame_no change */
131 __u16 frame_no; /* current frame number */
wdenk80885a92004-02-26 23:46:20 +0000132 __u32 done_head; /* info returned for an interrupt */
133 u8 reserved_for_hc[116];
Peter Tyserf9a109b2009-04-20 11:08:46 -0500134} __attribute__((aligned(256)));
wdenk80885a92004-02-26 23:46:20 +0000135
136
137/*
138 * Maximum number of root hub ports.
139 */
140#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
141
142/*
143 * This is the structure of the OHCI controller's memory mapped I/O
144 * region. This is Memory Mapped I/O. You must use the readl() and
145 * writel() macros defined in asm/io.h to access these!!
146 */
147struct ohci_regs {
148 /* control and status registers */
149 __u32 revision;
150 __u32 control;
151 __u32 cmdstatus;
152 __u32 intrstatus;
153 __u32 intrenable;
154 __u32 intrdisable;
155 /* memory pointers */
156 __u32 hcca;
157 __u32 ed_periodcurrent;
158 __u32 ed_controlhead;
159 __u32 ed_controlcurrent;
160 __u32 ed_bulkhead;
161 __u32 ed_bulkcurrent;
162 __u32 donehead;
163 /* frame counters */
164 __u32 fminterval;
165 __u32 fmremaining;
166 __u32 fmnumber;
167 __u32 periodicstart;
168 __u32 lsthresh;
169 /* Root hub ports */
170 struct ohci_roothub_regs {
171 __u32 a;
172 __u32 b;
173 __u32 status;
174 __u32 portstatus[MAX_ROOT_PORTS];
175 } roothub;
Peter Tyserf9a109b2009-04-20 11:08:46 -0500176} __attribute__((aligned(32)));
wdenk80885a92004-02-26 23:46:20 +0000177
178
179/* OHCI CONTROL AND STATUS REGISTER MASKS */
180
181/*
182 * HcControl (control) register masks
183 */
184#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
185#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
186#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
187#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
188#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
189#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
190#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
191#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
192#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
193
194/* pre-shifted values for HCFS */
195# define OHCI_USB_RESET (0 << 6)
196# define OHCI_USB_RESUME (1 << 6)
197# define OHCI_USB_OPER (2 << 6)
198# define OHCI_USB_SUSPEND (3 << 6)
199
200/*
201 * HcCommandStatus (cmdstatus) register masks
202 */
203#define OHCI_HCR (1 << 0) /* host controller reset */
204#define OHCI_CLF (1 << 1) /* control list filled */
205#define OHCI_BLF (1 << 2) /* bulk list filled */
206#define OHCI_OCR (1 << 3) /* ownership change request */
207#define OHCI_SOC (3 << 16) /* scheduling overrun count */
208
209/*
210 * masks used with interrupt registers:
211 * HcInterruptStatus (intrstatus)
212 * HcInterruptEnable (intrenable)
213 * HcInterruptDisable (intrdisable)
214 */
215#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
216#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
217#define OHCI_INTR_SF (1 << 2) /* start frame */
218#define OHCI_INTR_RD (1 << 3) /* resume detect */
219#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
220#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
221#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
222#define OHCI_INTR_OC (1 << 30) /* ownership change */
223#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
224
225
226/* Virtual Root HUB */
227struct virt_root_hub {
228 int devnum; /* Address of Root Hub endpoint */
229 void *dev; /* was urb */
230 void *int_addr;
231 int send;
232 int interval;
233};
234
235/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
236
237/* destination of request */
238#define RH_INTERFACE 0x01
239#define RH_ENDPOINT 0x02
240#define RH_OTHER 0x03
241
242#define RH_CLASS 0x20
243#define RH_VENDOR 0x40
244
245/* Requests: bRequest << 8 | bmRequestType */
246#define RH_GET_STATUS 0x0080
247#define RH_CLEAR_FEATURE 0x0100
248#define RH_SET_FEATURE 0x0300
249#define RH_SET_ADDRESS 0x0500
250#define RH_GET_DESCRIPTOR 0x0680
251#define RH_SET_DESCRIPTOR 0x0700
252#define RH_GET_CONFIGURATION 0x0880
253#define RH_SET_CONFIGURATION 0x0900
254#define RH_GET_STATE 0x0280
255#define RH_GET_INTERFACE 0x0A80
256#define RH_SET_INTERFACE 0x0B00
257#define RH_SYNC_FRAME 0x0C80
258/* Our Vendor Specific Request */
259#define RH_SET_EP 0x2000
260
261
262/* Hub port features */
263#define RH_PORT_CONNECTION 0x00
264#define RH_PORT_ENABLE 0x01
265#define RH_PORT_SUSPEND 0x02
266#define RH_PORT_OVER_CURRENT 0x03
267#define RH_PORT_RESET 0x04
268#define RH_PORT_POWER 0x08
269#define RH_PORT_LOW_SPEED 0x09
270
271#define RH_C_PORT_CONNECTION 0x10
272#define RH_C_PORT_ENABLE 0x11
273#define RH_C_PORT_SUSPEND 0x12
274#define RH_C_PORT_OVER_CURRENT 0x13
275#define RH_C_PORT_RESET 0x14
276
277/* Hub features */
278#define RH_C_HUB_LOCAL_POWER 0x00
279#define RH_C_HUB_OVER_CURRENT 0x01
280
281#define RH_DEVICE_REMOTE_WAKEUP 0x00
282#define RH_ENDPOINT_STALL 0x01
283
284#define RH_ACK 0x01
285#define RH_REQ_ERR -1
286#define RH_NACK 0x00
287
288
289/* OHCI ROOT HUB REGISTER MASKS */
290
291/* roothub.portstatus [i] bits */
292#define RH_PS_CCS 0x00000001 /* current connect status */
293#define RH_PS_PES 0x00000002 /* port enable status*/
294#define RH_PS_PSS 0x00000004 /* port suspend status */
295#define RH_PS_POCI 0x00000008 /* port over current indicator */
296#define RH_PS_PRS 0x00000010 /* port reset status */
297#define RH_PS_PPS 0x00000100 /* port power status */
298#define RH_PS_LSDA 0x00000200 /* low speed device attached */
299#define RH_PS_CSC 0x00010000 /* connect status change */
300#define RH_PS_PESC 0x00020000 /* port enable status change */
301#define RH_PS_PSSC 0x00040000 /* port suspend status change */
302#define RH_PS_OCIC 0x00080000 /* over current indicator change */
303#define RH_PS_PRSC 0x00100000 /* port reset status change */
304
305/* roothub.status bits */
306#define RH_HS_LPS 0x00000001 /* local power status */
307#define RH_HS_OCI 0x00000002 /* over current indicator */
308#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
309#define RH_HS_LPSC 0x00010000 /* local power status change */
310#define RH_HS_OCIC 0x00020000 /* over current indicator change */
311#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
312
313/* roothub.b masks */
314#define RH_B_DR 0x0000ffff /* device removable flags */
315#define RH_B_PPCM 0xffff0000 /* port power control mask */
316
317/* roothub.a masks */
318#define RH_A_NDP (0xff << 0) /* number of downstream ports */
319#define RH_A_PSM (1 << 8) /* power switching mode */
320#define RH_A_NPS (1 << 9) /* no power switching */
321#define RH_A_DT (1 << 10) /* device type (mbz) */
322#define RH_A_OCPM (1 << 11) /* over current protection mode */
323#define RH_A_NOCP (1 << 12) /* no over current protection */
324#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
325
326/* urb */
327#define N_URB_TD 48
328typedef struct
329{
330 ed_t *ed;
331 __u16 length; /* number of tds associated with this request */
332 __u16 td_cnt; /* number of tds already serviced */
333 int state;
334 unsigned long pipe;
335 int actual_length;
336 td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
337} urb_priv_t;
338#define URB_DEL 1
339
340/*
341 * This is the full ohci controller description
342 *
343 * Note how the "proper" USB information is just
344 * a subset of what the full implementation needs. (Linus)
345 */
346
347
348typedef struct ohci {
349 struct ohci_hcca *hcca; /* hcca */
350 /*dma_addr_t hcca_dma;*/
351
352 int irq;
353 int disabled; /* e.g. got a UE, we're hung */
354 int sleeping;
355 unsigned long flags; /* for HC bugs */
356
357 struct ohci_regs *regs; /* OHCI controller's memory */
358
359 ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
360 ed_t *ed_bulktail; /* last endpoint of bulk list */
361 ed_t *ed_controltail; /* last endpoint of control list */
362 int intrstatus;
363 __u32 hc_control; /* copy of the hc control reg */
364 struct usb_device *dev[32];
365 struct virt_root_hub rh;
366
367 const char *slot_name;
368} ohci_t;
369
370#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
371
372struct ohci_device {
373 ed_t ed[NUM_EDS];
374 int ed_cnt;
375};
376
377/* hcd */
378/* endpoint */
379static int ep_link(ohci_t * ohci, ed_t * ed);
380static int ep_unlink(ohci_t * ohci, ed_t * ed);
381static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
382
383/*-------------------------------------------------------------------------*/
384
385/* we need more TDs than EDs */
386#define NUM_TD 64
387
388/* +1 so we can align the storage */
389td_t gtd[NUM_TD+1];
390/* pointers to aligned storage */
391td_t *ptd;
392
393/* TDs ... */
394static inline struct td *
395td_alloc (struct usb_device *usb_dev)
396{
397 int i;
398 struct td *td;
399
400 td = NULL;
401 for (i = 0; i < NUM_TD; i++)
402 {
403 if (ptd[i].usb_dev == NULL)
404 {
405 td = &ptd[i];
406 td->usb_dev = usb_dev;
407 break;
408 }
409 }
410
411 return td;
412}
413
414static inline void
415ed_free (struct ed *ed)
416{
417 ed->usb_dev = NULL;
418}