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wdenkd9fd6ff2002-10-11 08:43:32 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
wdenkd9fd6ff2002-10-11 08:43:32 +000032 * High Level Configuration Options
33 * (easy to change)
34 */
35#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
36#define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */
37
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39
40/*
41 * Size of malloc() pool
42 */
wdenk699b13a2002-11-03 18:03:52 +000043#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenka8c7c702003-12-06 19:49:23 +000044#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenkd9fd6ff2002-10-11 08:43:32 +000045
46/*
47 * Hardware drivers
48 */
49#define CONFIG_DRIVER_SMC91111
50#define CONFIG_SMC91111_BASE 0x10000300
51#define CONFIG_SMC91111_EXT_PHY
52#define CONFIG_SMC_USE_32_BIT
53
54/*
55 * select serial console configuration
56 */
57#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
58
59/* allow to overwrite serial and ethaddr */
60#define CONFIG_ENV_OVERWRITE
61
62#define CONFIG_BAUDRATE 115200
63
64#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
65
66/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
67#include <cmd_confdefs.h>
68
69#define CONFIG_BOOTDELAY 3
70#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200"
71#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
72#define CONFIG_NETMASK 255.255.0.0
73#define CONFIG_IPADDR 192.168.0.21
74#define CONFIG_SERVERIP 192.168.0.250
75#define CONFIG_BOOTCOMMAND "bootm 40000"
76#define CONFIG_CMDLINE_TAG
77
78/*
79 * Miscellaneous configurable options
80 */
81#define CFG_LONGHELP /* undef to save memory */
82#define CFG_PROMPT "=> " /* Monitor Command Prompt */
83#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
84#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
85#define CFG_MAXARGS 16 /* max number of command args */
86#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
87
88#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
89#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
90
91#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
92
93#define CFG_LOAD_ADDR 0xa2000000 /* default load address */
94
95#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
96#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
97
wdenk8bde7f72003-06-27 21:31:46 +000098 /* valid baudrates */
wdenkd9fd6ff2002-10-11 08:43:32 +000099#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
100
101/*
102 * Stack sizes
103 *
104 * The stack sizes are set up in start.S using the settings below
105 */
106#define CONFIG_STACKSIZE (128*1024) /* regular stack */
107#ifdef CONFIG_USE_IRQ
108#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
109#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
110#endif
111
112/*
113 * Physical Memory Map
114 */
115#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
116#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
117#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
118#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
119#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
120#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
121#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
122#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
123#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
124
125#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
126#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
127#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
128
129#define CFG_DRAM_BASE 0xa0000000
130#define CFG_DRAM_SIZE 0x04000000
131
132#define CFG_FLASH_BASE PHYS_FLASH_1
133
134/*
135 * FLASH and environment organization
136 */
137#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
138#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
139
140/* timeout values are in ticks */
141#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
142#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
143
144#define CFG_ENV_IS_IN_FLASH 1
145#define CFG_ENV_ADDR 0x00020000 /* absolute address for now */
146#define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
147
148/******************************************************************************
149 *
150 * CPU specific defines
151 *
152 ******************************************************************************/
153
154/*
155 * GPIO settings
156 *
157 * GPIO pin assignments
158 * GPIO Name Dir Out AF
159 * 0 NC
160 * 1 NC
161 * 2 SIRQ1 I
162 * 3 SIRQ2 I
163 * 4 SIRQ3 I
164 * 5 DMAACK1 O 0
165 * 6 DMAACK2 O 0
166 * 7 DMAACK3 O 0
167 * 8 TC1 O 0
168 * 9 TC2 O 0
169 * 10 TC3 O 0
170 * 11 nDMAEN O 1
171 * 12 AENCTRL O 0
172 * 13 PLDTC O 0
173 * 14 ETHIRQ I
174 * 15 NC
175 * 16 NC
176 * 17 NC
177 * 18 RDY I
178 * 19 DMASIO I
179 * 20 ETHIRQ NC
180 * 21 NC
181 * 22 PGMEN O 1 FIXME for debug only enable flash
182 * 23 NC
183 * 24 NC
184 * 25 NC
185 * 26 NC
186 * 27 NC
187 * 28 NC
188 * 29 NC
189 * 30 NC
190 * 31 NC
191 * 32 NC
192 * 33 NC
193 * 34 FFRXD I 01
194 * 35 FFCTS I 01
195 * 36 FFDCD I 01
196 * 37 FFDSR I 01
197 * 38 FFRI I 01
198 * 39 FFTXD O 1 10
199 * 40 FFDTR O 0 10
200 * 41 FFRTS O 0 10
201 * 42 RS232FOFF O 0 00
202 * 43 NC
203 * 44 NC
204 * 45 IRSL0 O 0
205 * 46 IRRX0 I 01
206 * 47 IRTX0 O 0 10
207 * 48 NC
208 * 49 nIOWE O 0
209 * 50 NC
210 * 51 NC
211 * 52 NC
212 * 53 NC
213 * 54 NC
214 * 55 NC
215 * 56 NC
216 * 57 NC
217 * 58 DKDIRQ I
218 * 59 NC
219 * 60 NC
220 * 61 NC
221 * 62 NC
222 * 63 NC
223 * 64 COMLED O 0
224 * 65 COMLED O 0
225 * 66 COMLED O 0
226 * 67 COMLED O 0
227 * 68 COMLED O 0
228 * 69 COMLED O 0
229 * 70 COMLED O 0
230 * 71 COMLED O 0
231 * 72 NC
232 * 73 NC
233 * 74 NC
234 * 75 NC
235 * 76 NC
236 * 77 NC
237 * 78 CSIO O 1
238 * 79 NC
239 * 80 CSETH O 1
240 *
241 * NOTE: All NC's are defined to be outputs
242 *
243 */
244/* Pin direction control */
245/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
246#define CFG_GPDR0_VAL 0xfff3bf02
247#define CFG_GPDR1_VAL 0xfbffbf83
248#define CFG_GPDR2_VAL 0x0001ffff
249/* Set and Clear registers */
250#define CFG_GPSR0_VAL 0x00400800
251#define CFG_GPSR1_VAL 0x00000480
252#define CFG_GPSR2_VAL 0x00014000
253#define CFG_GPCR0_VAL 0x00000000
254#define CFG_GPCR1_VAL 0x00000000
255#define CFG_GPCR2_VAL 0x00000000
256/* Edge detect registers (these are set by the kernel) */
257#define CFG_GRER0_VAL 0x00000000
258#define CFG_GRER1_VAL 0x00000000
259#define CFG_GRER2_VAL 0x00000000
260#define CFG_GFER0_VAL 0x00000000
261#define CFG_GFER1_VAL 0x00000000
262#define CFG_GFER2_VAL 0x00000000
263/* Alternate function registers */
264#define CFG_GAFR0_L_VAL 0x00000000
265#define CFG_GAFR0_U_VAL 0x00000010
266#define CFG_GAFR1_L_VAL 0x900a9550
267#define CFG_GAFR1_U_VAL 0x00000008
268#define CFG_GAFR2_L_VAL 0x20000000
269#define CFG_GAFR2_U_VAL 0x00000002
270
271/*
272 * Clocks, power control and interrupts
273 */
274#define CFG_PSSR_VAL 0x00000020
275#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
276#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
277#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
278
279/* FIXME
280 *
281 * RTC settings
282 * Watchdog
283 *
284 */
285
286/*
287 * Memory settings
288 *
289 * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
290 * Verify timings on all
291 */
292#define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */
293/*#define CFG_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */
294#define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */
295#define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */
296#ifdef REDBOOT_WAY
297#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
298#define CFG_MDMRS_VAL 0x00000000
299#define CFG_MDREFR_VAL 0x00018018
300#else
301#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
302#define CFG_MDMRS_VAL 0x00000000
wdenk400558b2005-04-02 23:52:25 +0000303#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
wdenkd9fd6ff2002-10-11 08:43:32 +0000304#endif
305
306/*
307 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
308 */
309#define CFG_MECR_VAL 0x00000000
310#define CFG_MCMEM0_VAL 0x00010504
311#define CFG_MCMEM1_VAL 0x00010504
312#define CFG_MCATT0_VAL 0x00010504
313#define CFG_MCATT1_VAL 0x00010504
314#define CFG_MCIO0_VAL 0x00004715
315#define CFG_MCIO1_VAL 0x00004715
316
317/* Board specific defines */
318
319/* LED defines */
320#define YELLOW 0x03
321#define RED 0x02
322#define GREEN 0x01
323#define OFF 0x00
324#define LED_IRDA0 0
325#define LED_IRDA1 2
326#define LED_IRDA2 4
327#define LED_IRDA3 6
328#define CRADLE_LED_SET_REG GPSR2
329#define CRADLE_LED_CLR_REG GPCR2
330
331/* SuperIO defines */
332#define CRADLE_SIO_INDEX 0x2e
333#define CRADLE_SIO_DATA 0x2f
334
335/* IO defines */
336#define CRADLE_CPLD_PHYS 0x08000000
337#define CRADLE_SIO1_PHYS 0x08100000
338#define CRADLE_SIO2_PHYS 0x08200000
339#define CRADLE_SIO3_PHYS 0x08300000
340#define CRADLE_ETH_PHYS 0x10000000
341
342#ifndef __ASSEMBLY__
343
344/* global prototypes */
345void led_code(int code, int color);
346
347#endif
348
349#endif /* __CONFIG_H */