blob: 400d979643caaf7cdaddc8ddfdae5dbf87a6169a [file] [log] [blame]
Shengzhou Liu8d67c362014-03-05 15:04:48 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T2080 RDB/PCIe board configuration file
9 */
10
11#ifndef __T2080RDB_H
12#define __T2080RDB_H
13
Shengzhou Liufb536872014-07-23 15:54:16 +080014#define CONFIG_SYS_GENERIC_BOARD
15#define CONFIG_DISPLAY_BOARDINFO
Shengzhou Liu8d67c362014-03-05 15:04:48 +080016#define CONFIG_T2080RDB
17#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18#define CONFIG_MMC
19#define CONFIG_SPI_FLASH
20#define CONFIG_USB_EHCI
21#define CONFIG_FSL_SATA_V2
22
23/* High Level Configuration Options */
24#define CONFIG_PHYS_64BIT
25#define CONFIG_BOOKE
26#define CONFIG_E500 /* BOOKE e500 family */
27#define CONFIG_E500MC /* BOOKE e500mc family */
28#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
29#define CONFIG_MP /* support multiple processors */
30#define CONFIG_ENABLE_36BIT_PHYS
31
32#ifdef CONFIG_PHYS_64BIT
33#define CONFIG_ADDR_MAP 1
34#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
35#endif
36
37#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
38#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
39#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053040#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Shengzhou Liu8d67c362014-03-05 15:04:48 +080041#define CONFIG_FSL_LAW /* Use common FSL init code */
42#define CONFIG_ENV_OVERWRITE
43
44#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamadae4536f82014-03-11 11:05:16 +090045#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
46#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080047
Shengzhou Liu4d666682014-04-18 16:43:40 +080048#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
49#define CONFIG_SPL_ENV_SUPPORT
50#define CONFIG_SPL_SERIAL_SUPPORT
51#define CONFIG_SPL_FLUSH_IMAGE
52#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
53#define CONFIG_SPL_LIBGENERIC_SUPPORT
54#define CONFIG_SPL_LIBCOMMON_SUPPORT
55#define CONFIG_SPL_I2C_SUPPORT
56#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
57#define CONFIG_FSL_LAW /* Use common FSL init code */
58#define CONFIG_SYS_TEXT_BASE 0x00201000
59#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
60#define CONFIG_SPL_PAD_TO 0x40000
61#define CONFIG_SPL_MAX_SIZE 0x28000
62#define RESET_VECTOR_OFFSET 0x27FFC
63#define BOOT_PAGE_OFFSET 0x27000
64#ifdef CONFIG_SPL_BUILD
65#define CONFIG_SPL_SKIP_RELOCATE
66#define CONFIG_SPL_COMMON_INIT_DDR
67#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
68#define CONFIG_SYS_NO_FLASH
Shengzhou Liu8d67c362014-03-05 15:04:48 +080069#endif
70
Shengzhou Liu4d666682014-04-18 16:43:40 +080071#ifdef CONFIG_NAND
72#define CONFIG_SPL_NAND_SUPPORT
73#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
74#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
75#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
76#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
77#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
78#define CONFIG_SPL_NAND_BOOT
79#endif
80
81#ifdef CONFIG_SPIFLASH
82#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
83#define CONFIG_SPL_SPI_SUPPORT
84#define CONFIG_SPL_SPI_FLASH_SUPPORT
85#define CONFIG_SPL_SPI_FLASH_MINIMAL
86#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
87#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
88#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
89#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
90#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
91#ifndef CONFIG_SPL_BUILD
92#define CONFIG_SYS_MPC85XX_NO_RESETVEC
93#endif
94#define CONFIG_SPL_SPI_BOOT
95#endif
96
97#ifdef CONFIG_SDCARD
98#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
99#define CONFIG_SPL_MMC_SUPPORT
100#define CONFIG_SPL_MMC_MINIMAL
101#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
102#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
103#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
104#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
105#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
106#ifndef CONFIG_SPL_BUILD
107#define CONFIG_SYS_MPC85XX_NO_RESETVEC
108#endif
109#define CONFIG_SPL_MMC_BOOT
110#endif
111
112#endif /* CONFIG_RAMBOOT_PBL */
113
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800114#define CONFIG_SRIO_PCIE_BOOT_MASTER
115#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
116/* Set 1M boot space */
117#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
118#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
119 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
120#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
121#define CONFIG_SYS_NO_FLASH
122#endif
123
124#ifndef CONFIG_SYS_TEXT_BASE
125#define CONFIG_SYS_TEXT_BASE 0xeff40000
126#endif
127
128#ifndef CONFIG_RESET_VECTOR_ADDRESS
129#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
130#endif
131
132/*
133 * These can be toggled for performance analysis, otherwise use default.
134 */
135#define CONFIG_SYS_CACHE_STASHING
136#define CONFIG_BTB /* toggle branch predition */
137#define CONFIG_DDR_ECC
138#ifdef CONFIG_DDR_ECC
139#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
140#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
141#endif
142
Shengzhou Liu4d666682014-04-18 16:43:40 +0800143#ifndef CONFIG_SYS_NO_FLASH
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800144#define CONFIG_FLASH_CFI_DRIVER
145#define CONFIG_SYS_FLASH_CFI
146#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
147#endif
148
149#if defined(CONFIG_SPIFLASH)
150#define CONFIG_SYS_EXTRA_ENV_RELOC
151#define CONFIG_ENV_IS_IN_SPI_FLASH
152#define CONFIG_ENV_SPI_BUS 0
153#define CONFIG_ENV_SPI_CS 0
154#define CONFIG_ENV_SPI_MAX_HZ 10000000
155#define CONFIG_ENV_SPI_MODE 0
156#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
157#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
158#define CONFIG_ENV_SECT_SIZE 0x10000
159#elif defined(CONFIG_SDCARD)
160#define CONFIG_SYS_EXTRA_ENV_RELOC
161#define CONFIG_ENV_IS_IN_MMC
162#define CONFIG_SYS_MMC_ENV_DEV 0
163#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liu4d666682014-04-18 16:43:40 +0800164#define CONFIG_ENV_OFFSET (512 * 0x800)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800165#elif defined(CONFIG_NAND)
166#define CONFIG_SYS_EXTRA_ENV_RELOC
167#define CONFIG_ENV_IS_IN_NAND
Shengzhou Liu4d666682014-04-18 16:43:40 +0800168#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800169#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
170#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
171#define CONFIG_ENV_IS_IN_REMOTE
172#define CONFIG_ENV_ADDR 0xffe20000
173#define CONFIG_ENV_SIZE 0x2000
174#elif defined(CONFIG_ENV_IS_NOWHERE)
175#define CONFIG_ENV_SIZE 0x2000
176#else
177#define CONFIG_ENV_IS_IN_FLASH
178#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
179#define CONFIG_ENV_SIZE 0x2000
180#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
181#endif
182
183#ifndef __ASSEMBLY__
184unsigned long get_board_sys_clk(void);
185unsigned long get_board_ddr_clk(void);
186#endif
187
188#define CONFIG_SYS_CLK_FREQ 66660000
189#define CONFIG_DDR_CLK_FREQ 133330000
190
191/*
192 * Config the L3 Cache as L3 SRAM
193 */
Shengzhou Liu4d666682014-04-18 16:43:40 +0800194#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
195#define CONFIG_SYS_L3_SIZE (512 << 10)
196#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
197#ifdef CONFIG_RAMBOOT_PBL
198#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
199#endif
200#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
201#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
202#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
203#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800204
205#define CONFIG_SYS_DCSRBAR 0xf0000000
206#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
207
208/* EEPROM */
209#define CONFIG_ID_EEPROM
210#define CONFIG_SYS_I2C_EEPROM_NXID
211#define CONFIG_SYS_EEPROM_BUS_NUM 0
212#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
Shengzhou Liuef531c72014-04-18 16:43:41 +0800213#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800214
215/*
216 * DDR Setup
217 */
218#define CONFIG_VERY_BIG_RAM
219#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
220#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
221#define CONFIG_DIMM_SLOTS_PER_CTLR 1
222#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
223#define CONFIG_DDR_SPD
224#define CONFIG_SYS_FSL_DDR3
225#undef CONFIG_FSL_DDR_INTERACTIVE
226#define CONFIG_SYS_SPD_BUS_NUM 0
227#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
228#define SPD_EEPROM_ADDRESS1 0x51
229#define SPD_EEPROM_ADDRESS2 0x52
230#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
231#define CTRL_INTLV_PREFERED cacheline
232
233/*
234 * IFC Definitions
235 */
236#define CONFIG_SYS_FLASH_BASE 0xe8000000
237#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
238#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
239#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
240 CSPR_PORT_SIZE_16 | \
241 CSPR_MSEL_NOR | \
242 CSPR_V)
243#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
244
245/* NOR Flash Timing Params */
246#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
247
248#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
249 FTIM0_NOR_TEADC(0x5) | \
250 FTIM0_NOR_TEAHC(0x5))
251#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
252 FTIM1_NOR_TRAD_NOR(0x1A) |\
253 FTIM1_NOR_TSEQRAD_NOR(0x13))
254#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
255 FTIM2_NOR_TCH(0x4) | \
256 FTIM2_NOR_TWPH(0x0E) | \
257 FTIM2_NOR_TWP(0x1c))
258#define CONFIG_SYS_NOR_FTIM3 0x0
259
260#define CONFIG_SYS_FLASH_QUIET_TEST
261#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
262
263#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
264#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
265#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
266#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
267#define CONFIG_SYS_FLASH_EMPTY_INFO
268#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
269
270/* CPLD on IFC */
271#define CONFIG_SYS_CPLD_BASE 0xffdf0000
272#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
273#define CONFIG_SYS_CSPR2_EXT (0xf)
274#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
275 | CSPR_PORT_SIZE_8 \
276 | CSPR_MSEL_GPCM \
277 | CSPR_V)
278#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
279#define CONFIG_SYS_CSOR2 0x0
280
281/* CPLD Timing parameters for IFC CS2 */
282#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
283 FTIM0_GPCM_TEADC(0x0e) | \
284 FTIM0_GPCM_TEAHC(0x0e))
285#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
286 FTIM1_GPCM_TRAD(0x1f))
287#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800288 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800289 FTIM2_GPCM_TWP(0x1f))
290#define CONFIG_SYS_CS2_FTIM3 0x0
291
292/* NAND Flash on IFC */
293#define CONFIG_NAND_FSL_IFC
294#define CONFIG_SYS_NAND_BASE 0xff800000
295#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
296
297#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
298#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
299 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
300 | CSPR_MSEL_NAND /* MSEL = NAND */ \
301 | CSPR_V)
302#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
303
304#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
305 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
306 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
307 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
308 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
309 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
310 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
311
312#define CONFIG_SYS_NAND_ONFI_DETECTION
313
314/* ONFI NAND Flash mode0 Timing Params */
315#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
316 FTIM0_NAND_TWP(0x18) | \
317 FTIM0_NAND_TWCHT(0x07) | \
318 FTIM0_NAND_TWH(0x0a))
319#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
320 FTIM1_NAND_TWBE(0x39) | \
321 FTIM1_NAND_TRR(0x0e) | \
322 FTIM1_NAND_TRP(0x18))
323#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
324 FTIM2_NAND_TREH(0x0a) | \
325 FTIM2_NAND_TWHRE(0x1e))
326#define CONFIG_SYS_NAND_FTIM3 0x0
327
328#define CONFIG_SYS_NAND_DDR_LAW 11
329#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
330#define CONFIG_SYS_MAX_NAND_DEVICE 1
331#define CONFIG_MTD_NAND_VERIFY_WRITE
332#define CONFIG_CMD_NAND
333#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
334
335#if defined(CONFIG_NAND)
336#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
337#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
338#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
339#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
340#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
341#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
342#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
343#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
344#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
345#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
346#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
347#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
348#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
349#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
350#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
351#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
352#else
353#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
354#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
355#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
356#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
357#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
358#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
359#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
360#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
361#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
362#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
363#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
364#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
365#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
366#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
367#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
368#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
369#endif
370
371#if defined(CONFIG_RAMBOOT_PBL)
372#define CONFIG_SYS_RAMBOOT
373#endif
374
Shengzhou Liu4d666682014-04-18 16:43:40 +0800375#ifdef CONFIG_SPL_BUILD
376#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
377#else
378#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
379#endif
380
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800381#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
382#define CONFIG_MISC_INIT_R
383#define CONFIG_HWCONFIG
384
385/* define to use L1 as initial stack */
386#define CONFIG_L1_INIT_RAM
387#define CONFIG_SYS_INIT_RAM_LOCK
388#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
389#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
390#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
391/* The assembler doesn't like typecast */
392#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
393 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
394 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
395#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
396#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
397 GENERATED_GBL_DATA_SIZE)
398#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530399#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800400#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
401
402/*
403 * Serial Port
404 */
405#define CONFIG_CONS_INDEX 1
406#define CONFIG_SYS_NS16550
407#define CONFIG_SYS_NS16550_SERIAL
408#define CONFIG_SYS_NS16550_REG_SIZE 1
409#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
410#define CONFIG_SYS_BAUDRATE_TABLE \
411 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
412#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
413#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
414#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
415#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
416
417/* Use the HUSH parser */
418#define CONFIG_SYS_HUSH_PARSER
419#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
420
421/* pass open firmware flat tree */
422#define CONFIG_OF_LIBFDT
423#define CONFIG_OF_BOARD_SETUP
424#define CONFIG_OF_STDOUT_VIA_ALIAS
425
426/* new uImage format support */
427#define CONFIG_FIT
428#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
429
430/*
431 * I2C
432 */
433#define CONFIG_SYS_I2C
434#define CONFIG_SYS_I2C_FSL
435#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
436#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
437#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
438#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
439#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
440#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
441#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
442#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
443#define CONFIG_SYS_FSL_I2C_SPEED 100000
444#define CONFIG_SYS_FSL_I2C2_SPEED 100000
445#define CONFIG_SYS_FSL_I2C3_SPEED 100000
446#define CONFIG_SYS_FSL_I2C4_SPEED 100000
447#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
448#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
449#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
450#define I2C_MUX_CH_DEFAULT 0x8
451
452
453/*
454 * RapidIO
455 */
456#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
457#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
458#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
459#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
460#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
461#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
462/*
463 * for slave u-boot IMAGE instored in master memory space,
464 * PHYS must be aligned based on the SIZE
465 */
Liu Gange4911812014-05-15 14:30:34 +0800466#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
467#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
468#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
469#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800470/*
471 * for slave UCODE and ENV instored in master memory space,
472 * PHYS must be aligned based on the SIZE
473 */
Liu Gange4911812014-05-15 14:30:34 +0800474#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800475#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
476#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
477
478/* slave core release by master*/
479#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
480#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
481
482/*
483 * SRIO_PCIE_BOOT - SLAVE
484 */
485#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
486#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
487#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
488 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
489#endif
490
491/*
492 * eSPI - Enhanced SPI
493 */
494#ifdef CONFIG_SPI_FLASH
495#define CONFIG_FSL_ESPI
496#define CONFIG_SPI_FLASH_STMICRO
497#define CONFIG_SPI_FLASH_BAR
498#define CONFIG_CMD_SF
499#define CONFIG_SF_DEFAULT_SPEED 10000000
500#define CONFIG_SF_DEFAULT_MODE 0
501#endif
502
503/*
504 * General PCI
505 * Memory space is mapped 1-1, but I/O space must start from 0.
506 */
507#define CONFIG_PCI /* Enable PCI/PCIE */
508#define CONFIG_PCIE1 /* PCIE controler 1 */
509#define CONFIG_PCIE2 /* PCIE controler 2 */
510#define CONFIG_PCIE3 /* PCIE controler 3 */
511#define CONFIG_PCIE4 /* PCIE controler 4 */
512#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
513#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
514/* controller 1, direct to uli, tgtid 3, Base address 20000 */
515#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
516#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
517#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
518#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
519#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
520#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
521#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
522#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
523
524/* controller 2, Slot 2, tgtid 2, Base address 201000 */
525#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
526#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
527#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
528#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
529#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
530#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
531#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
532#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
533
534/* controller 3, Slot 1, tgtid 1, Base address 202000 */
535#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
536#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
537#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
538#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
539#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
540#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
541#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
542#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
543
544/* controller 4, Base address 203000 */
545#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
546#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
547#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
548#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
549#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
550#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
551#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
552
553#ifdef CONFIG_PCI
554#define CONFIG_PCI_INDIRECT_BRIDGE
555#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
556#define CONFIG_NET_MULTI
557#define CONFIG_E1000
558#define CONFIG_PCI_PNP /* do pci plug-and-play */
559#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
560#define CONFIG_DOS_PARTITION
561#endif
562
563/* Qman/Bman */
564#ifndef CONFIG_NOBQFMAN
565#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
566#define CONFIG_SYS_BMAN_NUM_PORTALS 18
567#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
568#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
569#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
570#define CONFIG_SYS_QMAN_NUM_PORTALS 18
571#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
572#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
573#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
574
575#define CONFIG_SYS_DPAA_FMAN
576#define CONFIG_SYS_DPAA_PME
577#define CONFIG_SYS_PMAN
578#define CONFIG_SYS_DPAA_DCE
579#define CONFIG_SYS_DPAA_RMAN /* RMan */
580#define CONFIG_SYS_INTERLAKEN
581
582/* Default address of microcode for the Linux Fman driver */
583#if defined(CONFIG_SPIFLASH)
584/*
585 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
586 * env, so we got 0x110000.
587 */
588#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Shengzhou Liuef531c72014-04-18 16:43:41 +0800589#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
590#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800591#define CONFIG_CORTINA_FW_ADDR 0x120000
592
593#elif defined(CONFIG_SDCARD)
594/*
595 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shengzhou Liu4d666682014-04-18 16:43:40 +0800596 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
597 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800598 */
599#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Shengzhou Liuef531c72014-04-18 16:43:41 +0800600#define CONFIG_SYS_CORTINA_FW_IN_MMC
Shengzhou Liu4d666682014-04-18 16:43:40 +0800601#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
602#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800603
604#elif defined(CONFIG_NAND)
605#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liuef531c72014-04-18 16:43:41 +0800606#define CONFIG_SYS_CORTINA_FW_IN_NAND
Shengzhou Liu4d666682014-04-18 16:43:40 +0800607#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
608#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800609#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
610/*
611 * Slave has no ucode locally, it can fetch this from remote. When implementing
612 * in two corenet boards, slave's ucode could be stored in master's memory
613 * space, the address can be mapped from slave TLB->slave LAW->
614 * slave SRIO or PCIE outbound window->master inbound window->
615 * master LAW->the ucode address in master's memory space.
616 */
617#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Shengzhou Liuef531c72014-04-18 16:43:41 +0800618#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
619#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800620#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
621#else
622#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Shengzhou Liuef531c72014-04-18 16:43:41 +0800623#define CONFIG_SYS_CORTINA_FW_IN_NOR
624#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800625#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
626#endif
627#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
628#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
629#endif /* CONFIG_NOBQFMAN */
630
631#ifdef CONFIG_SYS_DPAA_FMAN
632#define CONFIG_FMAN_ENET
633#define CONFIG_PHYLIB_10G
634#define CONFIG_PHY_CORTINA
635#define CONFIG_PHY_AQ1202
636#define CONFIG_PHY_REALTEK
637#define CONFIG_CORTINA_FW_LENGTH 0x40000
638#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
639#define RGMII_PHY2_ADDR 0x02
640#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
641#define CORTINA_PHY_ADDR2 0x0d
642#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
643#define FM1_10GEC4_PHY_ADDR 0x01
644#endif
645
646
647#ifdef CONFIG_FMAN_ENET
648#define CONFIG_MII /* MII PHY management */
649#define CONFIG_ETHPRIME "FM1@DTSEC3"
650#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
651#endif
652
653/*
654 * SATA
655 */
656#ifdef CONFIG_FSL_SATA_V2
657#define CONFIG_LIBATA
658#define CONFIG_FSL_SATA
659#define CONFIG_SYS_SATA_MAX_DEVICE 2
660#define CONFIG_SATA1
661#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
662#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
663#define CONFIG_SATA2
664#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
665#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
666#define CONFIG_LBA48
667#define CONFIG_CMD_SATA
668#define CONFIG_DOS_PARTITION
669#define CONFIG_CMD_EXT2
670#endif
671
672/*
673 * USB
674 */
675#ifdef CONFIG_USB_EHCI
676#define CONFIG_CMD_USB
677#define CONFIG_USB_STORAGE
678#define CONFIG_USB_EHCI_FSL
679#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
680#define CONFIG_CMD_EXT2
681#define CONFIG_HAS_FSL_DR_USB
682#endif
683
684/*
685 * SDHC
686 */
687#ifdef CONFIG_MMC
688#define CONFIG_CMD_MMC
689#define CONFIG_FSL_ESDHC
690#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
691#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
692#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
693#define CONFIG_GENERIC_MMC
694#define CONFIG_CMD_EXT2
695#define CONFIG_CMD_FAT
696#define CONFIG_DOS_PARTITION
697#endif
698
699/*
Shengzhou Liu4feac1c2014-04-02 14:28:35 +0800700 * Dynamic MTD Partition support with mtdparts
701 */
702#ifndef CONFIG_SYS_NO_FLASH
703#define CONFIG_MTD_DEVICE
704#define CONFIG_MTD_PARTITIONS
705#define CONFIG_CMD_MTDPARTS
706#define CONFIG_FLASH_CFI_MTD
707#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
708 "spi0=spife110000.1"
709#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
710 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
711 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
712 "1m(uboot),5m(kernel),128k(dtb),-(user)"
713#endif
714
715/*
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800716 * Environment
717 */
718
719/*
720 * Command line configuration.
721 */
722#include <config_cmd_default.h>
723
724#define CONFIG_CMD_DHCP
725#define CONFIG_CMD_ELF
Shengzhou Liuc665c472014-04-24 11:10:09 +0800726#define CONFIG_CMD_ERRATA
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800727#define CONFIG_CMD_MII
728#define CONFIG_CMD_I2C
729#define CONFIG_CMD_PING
730#define CONFIG_CMD_ECHO
731#define CONFIG_CMD_SETEXPR
732#define CONFIG_CMD_REGINFO
733#define CONFIG_CMD_BDI
734
735#ifdef CONFIG_PCI
736#define CONFIG_CMD_PCI
737#define CONFIG_CMD_NET
738#endif
739
Ruchika Gupta737537e2014-10-15 11:35:31 +0530740/* Hash command with SHA acceleration supported in hardware */
741#ifdef CONFIG_FSL_CAAM
742#define CONFIG_CMD_HASH
743#define CONFIG_SHA_HW_ACCEL
744#endif
745
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800746/*
747 * Miscellaneous configurable options
748 */
749#define CONFIG_SYS_LONGHELP /* undef to save memory */
750#define CONFIG_CMDLINE_EDITING /* Command-line editing */
751#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
752#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
753#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
754#ifdef CONFIG_CMD_KGDB
755#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
756#else
757#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
758#endif
759#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
760#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
761#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800762
763/*
764 * For booting Linux, the board info and command line data
765 * have to be in the first 64 MB of memory, since this is
766 * the maximum mapped by the Linux kernel during initialization.
767 */
768#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
769#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
770
771#ifdef CONFIG_CMD_KGDB
772#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
773#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
774#endif
775
776/*
777 * Environment Configuration
778 */
779#define CONFIG_ROOTPATH "/opt/nfsroot"
780#define CONFIG_BOOTFILE "uImage"
781#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
782
783/* default location for tftp and bootm */
784#define CONFIG_LOADADDR 1000000
785#define CONFIG_BAUDRATE 115200
786#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
787#define __USB_PHY_TYPE utmi
788
789#define CONFIG_EXTRA_ENV_SETTINGS \
790 "hwconfig=fsl_ddr:" \
791 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
792 "bank_intlv=auto;" \
793 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
794 "netdev=eth0\0" \
795 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
796 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
797 "tftpflash=tftpboot $loadaddr $uboot && " \
798 "protect off $ubootaddr +$filesize && " \
799 "erase $ubootaddr +$filesize && " \
800 "cp.b $loadaddr $ubootaddr $filesize && " \
801 "protect on $ubootaddr +$filesize && " \
802 "cmp.b $loadaddr $ubootaddr $filesize\0" \
803 "consoledev=ttyS0\0" \
804 "ramdiskaddr=2000000\0" \
805 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
806 "fdtaddr=c00000\0" \
807 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500808 "bdev=sda3\0"
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800809
810/*
811 * For emulation this causes u-boot to jump to the start of the
812 * proof point app code automatically
813 */
814#define CONFIG_PROOF_POINTS \
815 "setenv bootargs root=/dev/$bdev rw " \
816 "console=$consoledev,$baudrate $othbootargs;" \
817 "cpu 1 release 0x29000000 - - -;" \
818 "cpu 2 release 0x29000000 - - -;" \
819 "cpu 3 release 0x29000000 - - -;" \
820 "cpu 4 release 0x29000000 - - -;" \
821 "cpu 5 release 0x29000000 - - -;" \
822 "cpu 6 release 0x29000000 - - -;" \
823 "cpu 7 release 0x29000000 - - -;" \
824 "go 0x29000000"
825
826#define CONFIG_HVBOOT \
827 "setenv bootargs config-addr=0x60000000; " \
828 "bootm 0x01000000 - 0x00f00000"
829
830#define CONFIG_ALU \
831 "setenv bootargs root=/dev/$bdev rw " \
832 "console=$consoledev,$baudrate $othbootargs;" \
833 "cpu 1 release 0x01000000 - - -;" \
834 "cpu 2 release 0x01000000 - - -;" \
835 "cpu 3 release 0x01000000 - - -;" \
836 "cpu 4 release 0x01000000 - - -;" \
837 "cpu 5 release 0x01000000 - - -;" \
838 "cpu 6 release 0x01000000 - - -;" \
839 "cpu 7 release 0x01000000 - - -;" \
840 "go 0x01000000"
841
842#define CONFIG_LINUX \
843 "setenv bootargs root=/dev/ram rw " \
844 "console=$consoledev,$baudrate $othbootargs;" \
845 "setenv ramdiskaddr 0x02000000;" \
846 "setenv fdtaddr 0x00c00000;" \
847 "setenv loadaddr 0x1000000;" \
848 "bootm $loadaddr $ramdiskaddr $fdtaddr"
849
850#define CONFIG_HDBOOT \
851 "setenv bootargs root=/dev/$bdev rw " \
852 "console=$consoledev,$baudrate $othbootargs;" \
853 "tftp $loadaddr $bootfile;" \
854 "tftp $fdtaddr $fdtfile;" \
855 "bootm $loadaddr - $fdtaddr"
856
857#define CONFIG_NFSBOOTCOMMAND \
858 "setenv bootargs root=/dev/nfs rw " \
859 "nfsroot=$serverip:$rootpath " \
860 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
861 "console=$consoledev,$baudrate $othbootargs;" \
862 "tftp $loadaddr $bootfile;" \
863 "tftp $fdtaddr $fdtfile;" \
864 "bootm $loadaddr - $fdtaddr"
865
866#define CONFIG_RAMBOOTCOMMAND \
867 "setenv bootargs root=/dev/ram rw " \
868 "console=$consoledev,$baudrate $othbootargs;" \
869 "tftp $ramdiskaddr $ramdiskfile;" \
870 "tftp $loadaddr $bootfile;" \
871 "tftp $fdtaddr $fdtfile;" \
872 "bootm $loadaddr $ramdiskaddr $fdtaddr"
873
874#define CONFIG_BOOTCOMMAND CONFIG_LINUX
875
876#ifdef CONFIG_SECURE_BOOT
877#include <asm/fsl_secure_boot.h>
Ruchika Gupta789490b2014-10-07 15:48:46 +0530878#define CONFIG_CMD_BLOB
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800879#undef CONFIG_CMD_USB
880#endif
881
882#endif /* __T2080RDB_H */