| Alex Dubov | a14a944 | 2011-01-23 21:59:10 -0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <asm/mmu.h> |
| 26 | |
| 27 | struct fsl_e_tlb_entry tlb_table[] = { |
| 28 | /* TLB 0 - for temp stack in cache */ |
| 29 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
| 30 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 31 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 32 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
| 33 | CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
| 34 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 35 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 36 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
| 37 | CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
| 38 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 39 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 40 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
| 41 | CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
| 42 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 43 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 44 | |
| 45 | /* |
| 46 | * TLB 0: 256M Non-cacheable, guarded |
| 47 | * 0xf0000000 256M LBC (FLASH included) |
| 48 | * Out of reset this entry is only 4K. |
| 49 | */ |
| 50 | SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, |
| 51 | CONFIG_SYS_LBC_OPTION_BASE_PHYS, |
| 52 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 53 | 0, 0, BOOKE_PAGESZ_256M, 1), |
| 54 | |
| 55 | /* |
| 56 | * TLB 1: 1M Non-cacheable, guarded |
| 57 | * 0xe000_0000 1M CCSRBAR |
| 58 | */ |
| 59 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
| 60 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 61 | 0, 1, BOOKE_PAGESZ_1M, 1), |
| 62 | |
| 63 | #ifdef CONFIG_SYS_SRIO1_MEM_PHYS |
| 64 | /* |
| 65 | * TLB 2: 256M Non-cacheable, guarded |
| 66 | */ |
| 67 | SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, |
| 68 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 69 | 0, 2, BOOKE_PAGESZ_256M, 1), |
| 70 | |
| 71 | /* |
| 72 | * TLB 3: 256M Non-cacheable, guarded |
| 73 | */ |
| 74 | SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, |
| 75 | CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000, |
| 76 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 77 | 0, 3, BOOKE_PAGESZ_256M, 1), |
| 78 | |
| 79 | #endif |
| 80 | }; |
| 81 | |
| 82 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |