blob: a687af0a0119e7c91f3dc65a938f4279484bba0b [file] [log] [blame]
Matthias Kaehlckecf3c1422010-02-01 21:29:48 +01001/*
2 * PLL setup for Cirrus edb93xx boards
3 *
4 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
5 *
6 * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/io.h>
29#include "pll_cfg.h"
30#include "early_udelay.h"
31
32void pll_cfg(void)
33{
34 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
35
36 /* setup PLL1 */
37 writel(CLKSET1_VAL, &syscon->clkset1);
38
39 /*
40 * flush the pipeline
41 * writing to CLKSET1 causes the EP93xx to enter standby for between
42 * 8 ms to 16 ms, until PLL1 stabilizes
43 */
44 asm("nop");
45 asm("nop");
46 asm("nop");
47 asm("nop");
48 asm("nop");
49
50 /* setup PLL2 */
51 writel(CLKSET2_VAL, &syscon->clkset2);
52
53 /*
54 * the user's guide recommends to wait at least 1 ms for PLL2 to
55 * stabilize
56 */
57 early_udelay(1000);
58}