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Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +02001/*
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +02002 * (C) Copyright 2000-2004
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +02003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +02004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_ARCH(powerpc)
25ENTRY(_start_440)
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +020026
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +020027SECTIONS
28{
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +020029 .resetvec 0xFFFFFFFC :
30 {
31 *(.resetvec)
32 } = 0xffff
33
34 .bootpg 0xFFFFF000 :
35 {
Stefan Roesea47a12b2010-04-15 16:07:28 +020036 arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +020037 } = 0xffff
38
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +020039 /* Read-only sections, merged into text segment: */
40 . = + SIZEOF_HEADERS;
41 .interp : { *(.interp) }
42 .hash : { *(.hash) }
43 .dynsym : { *(.dynsym) }
44 .dynstr : { *(.dynstr) }
45 .rel.text : { *(.rel.text) }
46 .rela.text : { *(.rela.text) }
47 .rel.data : { *(.rel.data) }
48 .rela.data : { *(.rela.data) }
49 .rel.rodata : { *(.rel.rodata) }
50 .rela.rodata : { *(.rela.rodata) }
51 .rel.got : { *(.rel.got) }
52 .rela.got : { *(.rela.got) }
53 .rel.ctors : { *(.rel.ctors) }
54 .rela.ctors : { *(.rela.ctors) }
55 .rel.dtors : { *(.rel.dtors) }
56 .rela.dtors : { *(.rela.dtors) }
57 .rel.bss : { *(.rel.bss) }
58 .rela.bss : { *(.rela.bss) }
59 .rel.plt : { *(.rel.plt) }
60 .rela.plt : { *(.rela.plt) }
61 .init : { *(.init) }
62 .plt : { *(.plt) }
63 .text :
64 {
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +020065 /* WARNING - the following is hand-optimized to fit within */
66 /* the sector layout of our flash chips! XXX FIXME XXX */
67
68
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +020069 *(.text)
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +020070 *(.got1)
71 }
72 _etext = .;
73 PROVIDE (etext = .);
74 .rodata :
75 {
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +020076 *(.eh_frame)
Trent Piephof62fb992009-02-18 15:22:05 -080077 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +020078 }
79 .fini : { *(.fini) } =0
80 .ctors : { *(.ctors) }
81 .dtors : { *(.dtors) }
82
83 /* Read-write section, merged into data segment: */
84 . = (. + 0x00FF) & 0xFFFFFF00;
85 _erotext = .;
86 PROVIDE (erotext = .);
87 .reloc :
88 {
89 *(.got)
90 _GOT2_TABLE_ = .;
91 *(.got2)
92 _FIXUP_TABLE_ = .;
93 *(.fixup)
94 }
95 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
96 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
97
98 .data :
99 {
100 *(.data)
101 *(.data1)
102 *(.sdata)
103 *(.sdata2)
104 *(.dynamic)
105 CONSTRUCTORS
106 }
107 _edata = .;
108 PROVIDE (edata = .);
109
110 . = .;
111 __u_boot_cmd_start = .;
112 .u_boot_cmd : { *(.u_boot_cmd) }
113 __u_boot_cmd_end = .;
114
115
116 . = .;
117 __start___ex_table = .;
118 __ex_table : { *(__ex_table) }
119 __stop___ex_table = .;
120
121 . = ALIGN(256);
122 __init_begin = .;
123 .text.init : { *(.text.init) }
124 .data.init : { *(.data.init) }
125 . = ALIGN(256);
126 __init_end = .;
127
128 __bss_start = .;
129 .bss (NOLOAD) :
130 {
131 *(.sbss) *(.scommon)
132 *(.dynbss)
133 *(.bss)
134 *(COMMON)
Selvamuthukumar9b827cf2008-10-16 22:54:03 +0530135 . = ALIGN(4);
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +0200136 }
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +0200137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138 ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +0200139
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +0200140 _end = . ;
141 PROVIDE (end = .);
142}