blob: 107f01a07ec7e53387a577b0e7771d59b9654bf8 [file] [log] [blame]
Heiko Schocher4e43b2e2010-07-07 12:26:34 +02001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 *
4 * (C) Copyright 2010
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher4e43b2e2010-07-07 12:26:34 +02008 */
9/*
10 * ve8313 board configuration file
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Kim Phillipsfdfaa292015-03-17 12:00:45 -050016#define CONFIG_SYS_GENERIC_BOARD
17#define CONFIG_DISPLAY_BOARDINFO
18
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020019/*
20 * High Level Configuration Options
21 */
22#define CONFIG_E300 1
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020023#define CONFIG_MPC831x 1
24#define CONFIG_MPC8313 1
25#define CONFIG_VE8313 1
26
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#ifndef CONFIG_SYS_TEXT_BASE
28#define CONFIG_SYS_TEXT_BASE 0xfe000000
29#endif
30
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020031#define CONFIG_PCI 1
Gabor Juhos842033e2013-05-30 07:06:12 +000032#define CONFIG_PCI_INDIRECT_BRIDGE 1
Kumar Galaa2243b82010-08-19 01:48:14 -050033#define CONFIG_FSL_ELBC 1
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020034
35#define CONFIG_BOARD_EARLY_INIT_F 1
36
37/*
38 * On-board devices
39 *
40 */
41#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
42
43#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
44
45#define CONFIG_SYS_IMMR 0xE0000000
46
47#define CONFIG_SYS_MEMTEST_START 0x00001000
48#define CONFIG_SYS_MEMTEST_END 0x07000000
49
50#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
51#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
52
53/*
54 * Device configurations
55 */
56
57/*
58 * DDR Setup
59 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050060#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020061#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
62#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
63
64/*
65 * Manually set up DDR parameters, as this board does not
66 * have the SPD connected to I2C.
67 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050068#define CONFIG_SYS_DDR_SIZE 128 /* MB */
Joe Hershberger2e651b22011-10-11 23:57:31 -050069#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020070 | CSCONFIG_AP \
Joe Hershberger2fef4022011-10-11 23:57:29 -050071 | CSCONFIG_ODT_RD_NEVER \
72 | CSCONFIG_ODT_WR_ALL \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050073 | CSCONFIG_ROW_BIT_13 \
74 | CSCONFIG_COL_BIT_10)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020075 /* 0x80840102 */
76
77#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050078#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
79 | (0 << TIMING_CFG0_WRT_SHIFT) \
80 | (3 << TIMING_CFG0_RRT_SHIFT) \
81 | (2 << TIMING_CFG0_WWT_SHIFT) \
82 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
83 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
84 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
85 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020086 /* 0x0e720802 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050087#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
88 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
89 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
90 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
91 | (6 << TIMING_CFG1_REFREC_SHIFT) \
92 | (2 << TIMING_CFG1_WRREC_SHIFT) \
93 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
94 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020095 /* 0x26256222 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050096#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
97 | (5 << TIMING_CFG2_CPO_SHIFT) \
98 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
99 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
100 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
101 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
102 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200103 /* 0x029028c7 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500104#define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
105 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200106 /* 0x03202000 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500107#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200108 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500109 | SDRAM_CFG_DBW_32)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200110 /* 0x43080000 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500111#define CONFIG_SYS_SDRAM_CFG2 0x00401000
112#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
113 | (0x0232 << SDRAM_MODE_SD_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200114 /* 0x44400232 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500115#define CONFIG_SYS_DDR_MODE_2 0x8000C000
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200116
117#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
118 /*0x02000000*/
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500119#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200120 | DDRCDR_PZ_NOMZ \
121 | DDRCDR_NZ_NOMZ \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500122 | DDRCDR_M_ODR)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200123 /* 0x73000002 */
124
125/*
126 * FLASH on the Local Bus
127 */
128#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
129#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
130#define CONFIG_SYS_FLASH_BASE 0xFE000000
131#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
132#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
133#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
134
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500135#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500136 | BR_PS_16 /* 16 bit */ \
137 | BR_MS_GPCM /* MSEL = GPCM */ \
138 | BR_V) /* valid */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200139#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500140 | OR_GPCM_CSNT \
141 | OR_GPCM_ACS_DIV4 \
142 | OR_GPCM_SCY_5 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500143 | OR_GPCM_TRLX_SET \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500144 | OR_GPCM_EAD)
145 /* 0xfe000c55 */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200146
147#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500148#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200149
150#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
151#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
152
153#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
154#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
155
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200156#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200157
158#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
159#define CONFIG_SYS_RAMBOOT
160#endif
161
162#define CONFIG_SYS_INIT_RAM_LOCK 1
163#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500164#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200165
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500166#define CONFIG_SYS_GBL_DATA_OFFSET \
167 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200168#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
169
170/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
171#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
172#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
173
174/*
175 * Local Bus LCRR and LBCR regs
176 */
177#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
178#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
179
180#define CONFIG_SYS_LBC_LBCR 0x00040000
181
182#define CONFIG_SYS_LBC_MRTPR 0x20000000
183
184/*
185 * NAND settings
186 */
187#define CONFIG_SYS_NAND_BASE 0x61000000
188#define CONFIG_SYS_MAX_NAND_DEVICE 1
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200189#define CONFIG_CMD_NAND 1
190#define CONFIG_NAND_FSL_ELBC 1
191#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
192
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500193#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
194 | BR_PS_8 \
195 | BR_DECC_CHK_GEN \
196 | BR_MS_FCM \
197 | BR_V) /* valid */
198 /* 0x61000c21 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500199#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500200 | OR_FCM_BCTLD \
201 | OR_FCM_CHT \
202 | OR_FCM_SCY_2 \
203 | OR_FCM_RST \
204 | OR_FCM_TRLX)
205 /* 0xffff90ac */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200206
207#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
208#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
209#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
210#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
211
212#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500213#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200214
215#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
216#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
217
218/* CS2 NvRAM */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500219#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
220 | BR_PS_8 \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200221 | BR_V)
222 /* 0x60000801 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500223#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500224 | OR_GPCM_CSNT \
225 | OR_GPCM_XACS \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200226 | OR_GPCM_SCY_3 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500227 | OR_GPCM_TRLX_SET \
228 | OR_GPCM_EHTR_SET \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200229 | OR_GPCM_EAD)
230 /* 0xfffe0937 */
231/* local bus read write buffer mapping SRAM@0x64000000 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500232#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
233 | BR_PS_16 \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200234 | BR_V)
235 /* 0x62001001 */
236
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500237#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500238 | OR_GPCM_CSNT \
239 | OR_GPCM_XACS \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200240 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500241 | OR_GPCM_TRLX_SET \
242 | OR_GPCM_EHTR_SET \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200243 | OR_GPCM_EAD)
244 /* 0xfe0009f7 */
245
246/* pass open firmware flat tree */
247#define CONFIG_OF_LIBFDT 1
248#define CONFIG_OF_BOARD_SETUP 1
249#define CONFIG_OF_STDOUT_VIA_ALIAS 1
250
251/*
252 * Serial Port
253 */
254#define CONFIG_CONS_INDEX 1
255#define CONFIG_SYS_NS16550
256#define CONFIG_SYS_NS16550_SERIAL
257#define CONFIG_SYS_NS16550_REG_SIZE 1
258#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
259
260#define CONFIG_SYS_BAUDRATE_TABLE \
261 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
262
263#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
264#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
265
266/* Use the HUSH parser */
267#define CONFIG_SYS_HUSH_PARSER
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200268
269#if defined(CONFIG_PCI)
270/*
271 * General PCI
272 * Addresses are mapped 1-1.
273 */
274#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
275#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
276#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
277#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
278#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
279#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500280#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
281#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
282#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200283
284#define CONFIG_PCI_PNP /* do pci plug-and-play */
285#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
286#endif
287
288/*
289 * TSEC
290 */
291#define CONFIG_TSEC_ENET /* TSEC ethernet support */
292
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200293
294#define CONFIG_TSEC1
295#ifdef CONFIG_TSEC1
296#define CONFIG_HAS_ETH0
297#define CONFIG_TSEC1_NAME "TSEC1"
298#define CONFIG_SYS_TSEC1_OFFSET 0x24000
299#define TSEC1_PHY_ADDR 0x01
300#define TSEC1_FLAGS 0
301#define TSEC1_PHYIDX 0
302#endif
303
304/* Options are: TSEC[0-1] */
305#define CONFIG_ETHPRIME "TSEC1"
306
307/*
308 * Environment
309 */
310#define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500311#define CONFIG_ENV_ADDR \
312 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200313#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
314#define CONFIG_ENV_SIZE 0x4000
315/* Address and size of Redundant Environment Sector */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500316#define CONFIG_ENV_OFFSET_REDUND \
317 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200318#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
319
320#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
321#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
322
323/*
324 * BOOTP options
325 */
326#define CONFIG_BOOTP_BOOTFILESIZE
327#define CONFIG_BOOTP_BOOTPATH
328#define CONFIG_BOOTP_GATEWAY
329#define CONFIG_BOOTP_HOSTNAME
330
331/*
332 * Command line configuration.
333 */
334#include <config_cmd_default.h>
335
336#define CONFIG_CMD_DHCP
337#define CONFIG_CMD_MII
338#define CONFIG_CMD_PING
339#define CONFIG_CMD_PCI
340
341#define CONFIG_CMDLINE_EDITING 1
342#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
343
344/*
345 * Miscellaneous configurable options
346 */
347#define CONFIG_SYS_LONGHELP /* undef to save memory */
348#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200349#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
350
351#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
352#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
353#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200354
355/*
356 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700357 * have to be in the first 256 MB of memory, since this is
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200358 * the maximum mapped by the Linux kernel during initialization.
359 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500360 /* Initial Memory map for Linux*/
361#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200362
363/* 0x64050000 */
364#define CONFIG_SYS_HRCW_LOW (\
365 0x20000000 /* reserved, must be set */ |\
366 HRCWL_DDRCM |\
367 HRCWL_CSB_TO_CLKIN_4X1 | \
368 HRCWL_CORE_TO_CSB_2_5X1)
369
370/* 0xa0600004 */
371#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
372 HRCWH_PCI_ARBITER_ENABLE | \
373 HRCWH_CORE_ENABLE | \
374 HRCWH_FROM_0X00000100 | \
375 HRCWH_BOOTSEQ_DISABLE |\
376 HRCWH_SW_WATCHDOG_DISABLE |\
377 HRCWH_ROM_LOC_LOCAL_16BIT | \
378 HRCWH_TSEC1M_IN_MII | \
379 HRCWH_BIG_ENDIAN | \
380 HRCWH_LALE_EARLY)
381
382/* System IO Config */
383#define CONFIG_SYS_SICRH (0x01000000 | \
384 SICRH_ETSEC2_B | \
385 SICRH_ETSEC2_C | \
386 SICRH_ETSEC2_D | \
387 SICRH_ETSEC2_E | \
388 SICRH_ETSEC2_F | \
389 SICRH_ETSEC2_G | \
390 SICRH_TSOBI1 | \
391 SICRH_TSOBI2)
392 /* 0x010fff03 */
393#define CONFIG_SYS_SICRL (SICRL_LBC | \
394 SICRL_SPI_A | \
395 SICRL_SPI_B | \
396 SICRL_SPI_C | \
397 SICRL_SPI_D | \
398 SICRL_ETSEC2_A)
399 /* 0x33fc0003) */
400
401#define CONFIG_SYS_HID0_INIT 0x000000000
402#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
403 HID0_ENABLE_INSTRUCTION_CACHE)
404
405#define CONFIG_SYS_HID2 HID2_HBE
406
407#define CONFIG_HIGH_BATS 1 /* High BATs supported */
408
409/* DDR @ 0x00000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500410#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500411#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
412 | BATU_BL_256M \
413 | BATU_VS \
414 | BATU_VP)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200415
416#if defined(CONFIG_PCI)
417/* PCI @ 0x80000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500418#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500419#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
420 | BATU_BL_256M \
421 | BATU_VS \
422 | BATU_VP)
423#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500424 | BATL_PP_RW \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500425 | BATL_CACHEINHIBIT \
426 | BATL_GUARDEDSTORAGE)
427#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
428 | BATU_BL_256M \
429 | BATU_VS \
430 | BATU_VP)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200431#else
432#define CONFIG_SYS_IBAT1L (0)
433#define CONFIG_SYS_IBAT1U (0)
434#define CONFIG_SYS_IBAT2L (0)
435#define CONFIG_SYS_IBAT2U (0)
436#endif
437
438/* PCI2 not supported on 8313 */
439#define CONFIG_SYS_IBAT3L (0)
440#define CONFIG_SYS_IBAT3U (0)
441#define CONFIG_SYS_IBAT4L (0)
442#define CONFIG_SYS_IBAT4U (0)
443
444/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500445#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500446 | BATL_PP_RW \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500447 | BATL_CACHEINHIBIT \
448 | BATL_GUARDEDSTORAGE)
449#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
450 | BATU_BL_256M \
451 | BATU_VS \
452 | BATU_VP)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200453
454/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500455#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200456#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
457
458/* FPGA, SRAM, NAND @ 0x60000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500459#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200460#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
461
462#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
463#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
464#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
465#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
466#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
467#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
468#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
469#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
470#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
471#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
472#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
473#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
474#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
475#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
476#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
477#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
478
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200479#define CONFIG_NETDEV eth0
480
481#define CONFIG_HOSTNAME ve8313
482#define CONFIG_UBOOTPATH ve8313/u-boot.bin
483
484#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
485#define CONFIG_BAUDRATE 115200
486
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200487#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200488 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
489 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
490 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200491 "u-boot_addr_r=100000\0" \
492 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200493 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
494 " +${filesize};" \
495 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
496 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500497 " ${filesize};" \
Marek Vasut5368c552012-09-23 17:41:24 +0200498 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200499
500#endif /* __CONFIG_H */