blob: 106d2e390ba8b096898e4ac95a29cea454c12ca2 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simekd7e269c2014-01-14 14:21:52 +01002/*
3 * Copyright (c) 2014 Xilinx, Inc. Michal Simek
4 * Copyright (c) 2004-2008 Texas Instruments
5 *
6 * (C) Copyright 2002
7 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
Michal Simekd7e269c2014-01-14 14:21:52 +01008 */
9
Tom Rini2f41ade2019-01-22 17:09:26 -050010MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
11 LENGTH = IMAGE_MAX_SIZE }
Michal Simekd7e269c2014-01-14 14:21:52 +010012MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
13 LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
14
15OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
16OUTPUT_ARCH(arm)
17ENTRY(_start)
18SECTIONS
19{
20 . = ALIGN(4);
21 .text :
22 {
23 __image_copy_start = .;
Peter Crosthwaitefb8d8762014-08-07 22:26:43 +100024 *(.vectors)
Michal Simekd7e269c2014-01-14 14:21:52 +010025 CPUDIR/start.o (.text*)
26 *(.text*)
27 } > .sram
28
29 . = ALIGN(4);
30 .rodata : {
31 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
32 } > .sram
33
34 . = ALIGN(4);
35 .data : {
36 *(.data*)
37 } > .sram
38
39 . = ALIGN(4);
Simon Glass71556fb2015-10-17 19:41:23 -060040 .u_boot_list : {
Tom Rinif8a48262016-03-15 17:56:29 -040041 KEEP(*(SORT(.u_boot_list*)));
Simon Glass71556fb2015-10-17 19:41:23 -060042 } > .sram
43
44 . = ALIGN(4);
Michal Simekd7e269c2014-01-14 14:21:52 +010045
Simon Glass71556fb2015-10-17 19:41:23 -060046 _image_binary_end = .;
Michal Simekd7e269c2014-01-14 14:21:52 +010047
48 _end = .;
49
50 /* Move BSS section to RAM because of FAT */
51 .bss (NOLOAD) : {
52 __bss_start = .;
53 *(.bss*)
54 . = ALIGN(4);
55 __bss_end = .;
56 } > .sdram
57
58 /DISCARD/ : { *(.dynsym) }
59 /DISCARD/ : { *(.dynstr*) }
60 /DISCARD/ : { *(.dynamic*) }
61 /DISCARD/ : { *(.plt*) }
62 /DISCARD/ : { *(.interp*) }
63 /DISCARD/ : { *(.gnu*) }
64}