Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Marek Vasut | 7d0299c | 2018-04-17 14:13:11 +0200 | [diff] [blame] | 2 | /* |
| 3 | * board/renesas/koelsch/koelsch_spl.c |
| 4 | * |
| 5 | * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> |
Marek Vasut | 7d0299c | 2018-04-17 14:13:11 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | 9a3b4ce | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 9 | #include <cpu_func.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 10 | #include <init.h> |
Marek Vasut | 7d0299c | 2018-04-17 14:13:11 +0200 | [diff] [blame] | 11 | #include <malloc.h> |
| 12 | #include <dm/platform_data/serial_sh.h> |
| 13 | #include <asm/processor.h> |
| 14 | #include <asm/mach-types.h> |
| 15 | #include <asm/io.h> |
Simon Glass | cd93d62 | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 16 | #include <linux/bitops.h> |
Marek Vasut | 7d0299c | 2018-04-17 14:13:11 +0200 | [diff] [blame] | 17 | #include <linux/errno.h> |
| 18 | #include <asm/arch/sys_proto.h> |
| 19 | #include <asm/gpio.h> |
| 20 | #include <asm/arch/rmobile.h> |
| 21 | #include <asm/arch/rcar-mstp.h> |
| 22 | |
| 23 | #include <spl.h> |
| 24 | |
| 25 | #define TMU0_MSTP125 BIT(25) |
| 26 | #define SCIF0_MSTP721 BIT(21) |
| 27 | #define QSPI_MSTP917 BIT(17) |
| 28 | |
| 29 | #define SD2CKCR 0xE615026C |
| 30 | #define SD_97500KHZ 0x7 |
| 31 | |
| 32 | struct reg_config { |
| 33 | u16 off; |
| 34 | u32 val; |
| 35 | }; |
| 36 | |
| 37 | static void dbsc_wait(u16 reg) |
| 38 | { |
| 39 | static const u32 dbsc3_0_base = DBSC3_0_BASE; |
| 40 | static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; |
| 41 | |
| 42 | while (!(readl(dbsc3_0_base + reg) & BIT(0))) |
| 43 | ; |
| 44 | |
| 45 | while (!(readl(dbsc3_1_base + reg) & BIT(0))) |
| 46 | ; |
| 47 | } |
| 48 | |
| 49 | static void spl_init_sys(void) |
| 50 | { |
| 51 | u32 r0 = 0; |
| 52 | |
| 53 | writel(0xa5a5a500, 0xe6020004); |
| 54 | writel(0xa5a5a500, 0xe6030004); |
| 55 | |
| 56 | asm volatile( |
| 57 | /* ICIALLU - Invalidate I$ to PoU */ |
| 58 | "mcr 15, 0, %0, cr7, cr5, 0 \n" |
| 59 | /* BPIALL - Invalidate branch predictors */ |
| 60 | "mcr 15, 0, %0, cr7, cr5, 6 \n" |
| 61 | /* Set SCTLR[IZ] */ |
| 62 | "mrc 15, 0, %0, cr1, cr0, 0 \n" |
| 63 | "orr %0, #0x1800 \n" |
| 64 | "mcr 15, 0, %0, cr1, cr0, 0 \n" |
| 65 | "isb sy \n" |
| 66 | :"=r"(r0)); |
| 67 | } |
| 68 | |
| 69 | static void spl_init_pfc(void) |
| 70 | { |
| 71 | static const struct reg_config pfc_with_unlock[] = { |
| 72 | { 0x0090, 0x60000000 }, |
| 73 | { 0x0094, 0x60000000 }, |
| 74 | { 0x0098, 0x00800200 }, |
| 75 | { 0x009c, 0x00000000 }, |
| 76 | { 0x0020, 0x00000000 }, |
| 77 | { 0x0024, 0x00000000 }, |
| 78 | { 0x0028, 0x000244c8 }, |
| 79 | { 0x002c, 0x00000000 }, |
| 80 | { 0x0030, 0x00002400 }, |
| 81 | { 0x0034, 0x01520000 }, |
| 82 | { 0x0038, 0x00724003 }, |
| 83 | { 0x003c, 0x00000000 }, |
| 84 | { 0x0040, 0x00000000 }, |
| 85 | { 0x0044, 0x00000000 }, |
| 86 | { 0x0048, 0x00000000 }, |
| 87 | { 0x004c, 0x00000000 }, |
| 88 | { 0x0050, 0x00000000 }, |
| 89 | { 0x0054, 0x00000000 }, |
| 90 | { 0x0058, 0x00000000 }, |
| 91 | { 0x005c, 0x00000000 }, |
| 92 | { 0x0160, 0x00000000 }, |
| 93 | { 0x0004, 0xffffffff }, |
| 94 | { 0x0008, 0x00ec3fff }, |
| 95 | { 0x000c, 0x3bc001e7 }, |
| 96 | { 0x0010, 0x5bffffff }, |
| 97 | { 0x0014, 0x1ffffffb }, |
| 98 | { 0x0018, 0x01bffff0 }, |
| 99 | { 0x001c, 0xcf7fffff }, |
| 100 | { 0x0074, 0x0381fc00 }, |
| 101 | }; |
| 102 | |
| 103 | static const struct reg_config pfc_without_unlock[] = { |
| 104 | { 0x0100, 0xffffffdf }, |
| 105 | { 0x0104, 0xc883c3ff }, |
| 106 | { 0x0108, 0x1201f3c9 }, |
| 107 | { 0x010c, 0x00000000 }, |
| 108 | { 0x0110, 0xffffeb04 }, |
| 109 | { 0x0114, 0xc003ffff }, |
| 110 | { 0x0118, 0x0800000f }, |
| 111 | { 0x011c, 0x001800f0 }, |
| 112 | }; |
| 113 | |
| 114 | static const u32 pfc_base = 0xe6060000; |
| 115 | |
| 116 | unsigned int i; |
| 117 | |
| 118 | for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { |
| 119 | writel(~pfc_with_unlock[i].val, pfc_base); |
| 120 | writel(pfc_with_unlock[i].val, |
| 121 | pfc_base | pfc_with_unlock[i].off); |
| 122 | } |
| 123 | |
| 124 | for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) |
| 125 | writel(pfc_without_unlock[i].val, |
| 126 | pfc_base | pfc_without_unlock[i].off); |
| 127 | } |
| 128 | |
| 129 | static void spl_init_gpio(void) |
| 130 | { |
| 131 | static const u16 gpio_offs[] = { |
| 132 | 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800 |
| 133 | }; |
| 134 | |
| 135 | static const struct reg_config gpio_set[] = { |
| 136 | { 0x2000, 0x04381000 }, |
| 137 | { 0x5000, 0x00000000 }, |
| 138 | { 0x5800, 0x000e0000 }, |
| 139 | |
| 140 | }; |
| 141 | |
| 142 | static const struct reg_config gpio_clr[] = { |
| 143 | { 0x1000, 0x00000000 }, |
| 144 | { 0x2000, 0x04381010 }, |
| 145 | { 0x3000, 0x00000000 }, |
| 146 | { 0x4000, 0x00000000 }, |
| 147 | { 0x5000, 0x00400000 }, |
| 148 | { 0x5400, 0x00000000 }, |
| 149 | { 0x5800, 0x000e0380 }, |
| 150 | }; |
| 151 | |
| 152 | static const u32 gpio_base = 0xe6050000; |
| 153 | |
| 154 | unsigned int i; |
| 155 | |
| 156 | for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) |
| 157 | writel(0, gpio_base | 0x20 | gpio_offs[i]); |
| 158 | |
| 159 | for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) |
| 160 | writel(0, gpio_base | 0x00 | gpio_offs[i]); |
| 161 | |
| 162 | for (i = 0; i < ARRAY_SIZE(gpio_set); i++) |
| 163 | writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); |
| 164 | |
| 165 | for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) |
| 166 | writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); |
| 167 | } |
| 168 | |
| 169 | static void spl_init_lbsc(void) |
| 170 | { |
| 171 | static const struct reg_config lbsc_config[] = { |
| 172 | { 0x00, 0x00000020 }, |
| 173 | { 0x08, 0x00002020 }, |
| 174 | { 0x30, 0x2a103320 }, |
| 175 | { 0x38, 0xff70ff70 }, |
| 176 | }; |
| 177 | |
| 178 | static const u16 lbsc_offs[] = { |
| 179 | 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 |
| 180 | }; |
| 181 | |
| 182 | static const u32 lbsc_base = 0xfec00200; |
| 183 | |
| 184 | unsigned int i; |
| 185 | |
| 186 | for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { |
| 187 | writel(lbsc_config[i].val, |
| 188 | lbsc_base | lbsc_config[i].off); |
| 189 | writel(lbsc_config[i].val, |
| 190 | lbsc_base | (lbsc_config[i].off + 4)); |
| 191 | } |
| 192 | |
| 193 | for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) |
| 194 | writel(0, lbsc_base | lbsc_offs[i]); |
| 195 | } |
| 196 | |
| 197 | static void spl_init_dbsc(void) |
| 198 | { |
| 199 | static const struct reg_config dbsc_config1[] = { |
| 200 | { 0x0018, 0x21000000 }, |
| 201 | { 0x0018, 0x11000000 }, |
| 202 | { 0x0018, 0x10000000 }, |
| 203 | { 0x0280, 0x0000a55a }, |
| 204 | { 0x0290, 0x00000010 }, |
| 205 | { 0x02a0, 0xf004649b }, |
| 206 | { 0x0020, 0x00000007 }, |
| 207 | { 0x0024, 0x0f030a02 }, |
| 208 | { 0x0030, 0x00000001 }, |
| 209 | { 0x00b0, 0x00000000 }, |
| 210 | { 0x0040, 0x0000000b }, |
| 211 | { 0x0044, 0x00000008 }, |
| 212 | { 0x0048, 0x00000000 }, |
| 213 | { 0x0050, 0x0000000b }, |
| 214 | { 0x0054, 0x000c000b }, |
| 215 | { 0x0058, 0x00000027 }, |
| 216 | { 0x005c, 0x0000001c }, |
| 217 | { 0x0060, 0x00000006 }, |
| 218 | { 0x0064, 0x00000020 }, |
| 219 | { 0x0068, 0x00000008 }, |
| 220 | { 0x006c, 0x0000000c }, |
| 221 | { 0x0070, 0x00000009 }, |
| 222 | { 0x0074, 0x00000012 }, |
| 223 | { 0x0078, 0x000000d0 }, |
| 224 | { 0x007c, 0x00140005 }, |
| 225 | { 0x0080, 0x00050004 }, |
| 226 | { 0x0084, 0x70233005 }, |
| 227 | { 0x0088, 0x000c0000 }, |
| 228 | { 0x008c, 0x00000300 }, |
| 229 | { 0x0090, 0x00000040 }, |
| 230 | { 0x0100, 0x00000001 }, |
| 231 | { 0x00c0, 0x00020001 }, |
| 232 | { 0x00c8, 0x20082008 }, |
| 233 | { 0x0380, 0x00020002 }, |
| 234 | { 0x0390, 0x0000001f }, |
| 235 | }; |
| 236 | |
| 237 | static const struct reg_config dbsc_config5[] = { |
| 238 | { 0x0244, 0x00000011 }, |
| 239 | { 0x0290, 0x00000006 }, |
| 240 | { 0x02a0, 0x0005c000 }, |
| 241 | { 0x0290, 0x00000003 }, |
| 242 | { 0x02a0, 0x0300c481 }, |
| 243 | { 0x0290, 0x00000023 }, |
| 244 | { 0x02a0, 0x00fdb6c0 }, |
| 245 | { 0x0290, 0x00000011 }, |
| 246 | { 0x02a0, 0x1000040b }, |
| 247 | { 0x0290, 0x00000012 }, |
| 248 | { 0x02a0, 0x9d9cbb66 }, |
| 249 | { 0x0290, 0x00000013 }, |
| 250 | { 0x02a0, 0x1a868400 }, |
| 251 | { 0x0290, 0x00000014 }, |
| 252 | { 0x02a0, 0x300214d8 }, |
| 253 | { 0x0290, 0x00000015 }, |
| 254 | { 0x02a0, 0x00000d70 }, |
| 255 | { 0x0290, 0x00000016 }, |
| 256 | { 0x02a0, 0x00000006 }, |
| 257 | { 0x0290, 0x00000017 }, |
| 258 | { 0x02a0, 0x00000018 }, |
| 259 | { 0x0290, 0x0000001a }, |
| 260 | { 0x02a0, 0x910035c7 }, |
| 261 | { 0x0290, 0x00000004 }, |
| 262 | }; |
| 263 | |
| 264 | static const struct reg_config dbsc_config6[] = { |
| 265 | { 0x0290, 0x00000001 }, |
| 266 | { 0x02a0, 0x00000181 }, |
| 267 | { 0x0018, 0x11000000 }, |
| 268 | { 0x0290, 0x00000004 }, |
| 269 | }; |
| 270 | |
| 271 | static const struct reg_config dbsc_config7[] = { |
| 272 | { 0x0290, 0x00000001 }, |
| 273 | { 0x02a0, 0x0000fe01 }, |
| 274 | { 0x0290, 0x00000004 }, |
| 275 | }; |
| 276 | |
| 277 | static const struct reg_config dbsc_config8[] = { |
| 278 | { 0x0304, 0x00000000 }, |
| 279 | { 0x00f4, 0x01004c20 }, |
| 280 | { 0x00f8, 0x014000aa }, |
| 281 | { 0x00e0, 0x00000140 }, |
| 282 | { 0x00e4, 0x00081860 }, |
| 283 | { 0x00e8, 0x00010000 }, |
| 284 | { 0x0014, 0x00000001 }, |
| 285 | { 0x0010, 0x00000001 }, |
| 286 | { 0x0280, 0x00000000 }, |
| 287 | }; |
| 288 | |
| 289 | static const u32 dbsc3_0_base = DBSC3_0_BASE; |
| 290 | static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; |
| 291 | unsigned int i; |
| 292 | |
| 293 | for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) { |
| 294 | writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); |
| 295 | writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off); |
| 296 | } |
| 297 | |
| 298 | dbsc_wait(0x240); |
| 299 | |
| 300 | for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) { |
| 301 | writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); |
| 302 | writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off); |
| 303 | } |
| 304 | |
| 305 | dbsc_wait(0x2a0); |
| 306 | |
| 307 | for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) { |
| 308 | writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); |
| 309 | writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off); |
| 310 | } |
| 311 | |
| 312 | dbsc_wait(0x2a0); |
| 313 | |
| 314 | for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) { |
| 315 | writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); |
| 316 | writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off); |
| 317 | } |
| 318 | |
| 319 | dbsc_wait(0x2a0); |
| 320 | |
| 321 | for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) { |
| 322 | writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); |
| 323 | writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off); |
| 324 | } |
| 325 | |
| 326 | } |
| 327 | |
| 328 | static void spl_init_qspi(void) |
| 329 | { |
| 330 | mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); |
| 331 | |
| 332 | static const u32 qspi_base = 0xe6b10000; |
| 333 | |
| 334 | writeb(0x08, qspi_base + 0x00); |
| 335 | writeb(0x00, qspi_base + 0x01); |
| 336 | writeb(0x06, qspi_base + 0x02); |
| 337 | writeb(0x01, qspi_base + 0x0a); |
| 338 | writeb(0x00, qspi_base + 0x0b); |
| 339 | writeb(0x00, qspi_base + 0x0c); |
| 340 | writeb(0x00, qspi_base + 0x0d); |
| 341 | writeb(0x00, qspi_base + 0x0e); |
| 342 | |
| 343 | writew(0xe080, qspi_base + 0x10); |
| 344 | |
| 345 | writeb(0xc0, qspi_base + 0x18); |
| 346 | writeb(0x00, qspi_base + 0x18); |
| 347 | writeb(0x00, qspi_base + 0x08); |
| 348 | writeb(0x48, qspi_base + 0x00); |
| 349 | } |
| 350 | |
| 351 | void board_init_f(ulong dummy) |
| 352 | { |
| 353 | int i; |
| 354 | |
| 355 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
| 356 | mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); |
| 357 | |
| 358 | /* |
| 359 | * SD0 clock is set to 97.5MHz by default. |
| 360 | * Set SD2 to the 97.5MHz as well. |
| 361 | */ |
| 362 | writel(SD_97500KHZ, SD2CKCR); |
| 363 | |
| 364 | spl_init_sys(); |
| 365 | spl_init_pfc(); |
| 366 | spl_init_gpio(); |
| 367 | spl_init_lbsc(); |
| 368 | |
| 369 | /* Unknown, likely ES1.0-specific delay */ |
| 370 | for (i = 0; i < 100000; i++) |
| 371 | asm volatile("nop"); |
| 372 | |
| 373 | spl_init_dbsc(); |
| 374 | spl_init_qspi(); |
| 375 | } |
| 376 | |
| 377 | void spl_board_init(void) |
| 378 | { |
| 379 | /* UART clocks enabled and gd valid - init serial console */ |
| 380 | preloader_console_init(); |
| 381 | } |
| 382 | |
| 383 | void board_boot_order(u32 *spl_boot_list) |
| 384 | { |
| 385 | const u32 jtag_magic = 0x1337c0de; |
| 386 | const u32 load_magic = 0xb33fc0de; |
| 387 | |
| 388 | /* |
| 389 | * If JTAG probe sets special word at 0xe6300020, then it must |
| 390 | * put U-Boot into RAM and SPL will start it from RAM. |
| 391 | */ |
| 392 | if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { |
| 393 | printf("JTAG boot detected!\n"); |
| 394 | |
| 395 | while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) |
| 396 | ; |
| 397 | |
| 398 | spl_boot_list[0] = BOOT_DEVICE_RAM; |
| 399 | spl_boot_list[1] = BOOT_DEVICE_NONE; |
| 400 | |
| 401 | return; |
| 402 | } |
| 403 | |
| 404 | /* Boot from SPI NOR with YMODEM UART fallback. */ |
| 405 | spl_boot_list[0] = BOOT_DEVICE_SPI; |
| 406 | spl_boot_list[1] = BOOT_DEVICE_UART; |
| 407 | spl_boot_list[2] = BOOT_DEVICE_NONE; |
| 408 | } |
| 409 | |
| 410 | void reset_cpu(ulong addr) |
| 411 | { |
| 412 | } |