blob: a3797b22c74c4b3198a0c270ed48daabc97a3ee5 [file] [log] [blame]
Rick Chena1f24872019-04-02 15:56:40 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019, Rick Chen <rick@andestech.com>
Sean Andersone86463f2020-09-28 10:52:24 -04004 * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
Rick Chena1f24872019-04-02 15:56:40 +08005 *
6 * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
7 * The PLMT block holds memory-mapped mtime register
8 * associated with timer tick.
9 */
10
11#include <common.h>
12#include <dm.h>
Sean Andersone86463f2020-09-28 10:52:24 -040013#include <timer.h>
Rick Chena1f24872019-04-02 15:56:40 +080014#include <asm/io.h>
Simon Glass0fd3d912020-12-22 19:30:28 -070015#include <dm/device-internal.h>
Simon Glass61b29b82020-02-03 07:36:15 -070016#include <linux/err.h>
Rick Chena1f24872019-04-02 15:56:40 +080017
18/* mtime register */
19#define MTIME_REG(base) ((ulong)(base))
20
Pragnesh Patelbc8d12b2021-01-17 18:11:25 +053021static u64 notrace andes_plmt_get_count(struct udevice *dev)
Rick Chena1f24872019-04-02 15:56:40 +080022{
Simon Glass0fd3d912020-12-22 19:30:28 -070023 return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
Rick Chena1f24872019-04-02 15:56:40 +080024}
25
Pragnesh Patelbc8d12b2021-01-17 18:11:25 +053026#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
27/**
28 * timer_early_get_rate() - Get the timer rate before driver model
29 */
30unsigned long notrace timer_early_get_rate(void)
31{
32 return RISCV_MMODE_TIMER_FREQ;
33}
34
35/**
36 * timer_early_get_count() - Get the timer count before driver model
37 *
38 */
39u64 notrace timer_early_get_count(void)
40{
41 return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
42}
43#endif
44
Sean Andersone86463f2020-09-28 10:52:24 -040045static const struct timer_ops andes_plmt_ops = {
46 .get_count = andes_plmt_get_count,
47};
48
49static int andes_plmt_probe(struct udevice *dev)
50{
Simon Glass0fd3d912020-12-22 19:30:28 -070051 dev_set_priv(dev, dev_read_addr_ptr(dev));
52 if (!dev_get_priv(dev))
Sean Andersone86463f2020-09-28 10:52:24 -040053 return -EINVAL;
54
55 return timer_timebase_fallback(dev);
56}
57
Rick Chena1f24872019-04-02 15:56:40 +080058static const struct udevice_id andes_plmt_ids[] = {
Sean Andersone86463f2020-09-28 10:52:24 -040059 { .compatible = "riscv,plmt0" },
Rick Chena1f24872019-04-02 15:56:40 +080060 { }
61};
62
63U_BOOT_DRIVER(andes_plmt) = {
64 .name = "andes_plmt",
Sean Andersone86463f2020-09-28 10:52:24 -040065 .id = UCLASS_TIMER,
Rick Chena1f24872019-04-02 15:56:40 +080066 .of_match = andes_plmt_ids,
Sean Andersone86463f2020-09-28 10:52:24 -040067 .ops = &andes_plmt_ops,
68 .probe = andes_plmt_probe,
Rick Chena1f24872019-04-02 15:56:40 +080069 .flags = DM_FLAG_PRE_RELOC,
70};