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Dave Liuac4b5622006-10-31 19:54:59 -06001Freescale MPC8360EMDS Board
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31. Board Switches and Jumpers
Wolfgang Denk53677ef2008-05-20 16:00:29 +020041.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
Dave Liuac4b5622006-10-31 19:54:59 -06005 For some reason, the HW designers describe the switch settings
6 in terms of 0 and 1, and then map that to physical switches where
7 the label "On" refers to logic 0 and "Off" is logic 1.
8
9 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
10 bits may contribute to signals that are numbered based at 0,
11 and some of those signals may be high-bit-number-0 too. Heed
12 well the names and labels and do not get confused.
13
14 "Off" == 1
15 "On" == 0
16
17 SW18 is switch 18 as silk-screened onto the board.
18 SW4[8] is the bit labled 8 on Switch 4.
19 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
20 SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
21 SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
22 and bits labeled 8 is set as "Off".
23
Dave Liu66dc2c22007-06-25 13:21:12 +0800241.1 There are three type boards for MPC8360E silicon up to now, They are
25
26 * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE)
27 * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT)
28 * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE)
29
301.2 For all the MPC8360EMDS Board
Dave Liuac4b5622006-10-31 19:54:59 -060031
32 First, make sure the board default setting is consistent with the
33 document shipped with your board. Then apply the following setting:
34 SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus)
35 SW4[1-8]= 0011_0000 (Flash boot on local bus)
36 SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH)
37 SW10[1-8]= 0000_1000 (core PLL setting)
38 SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
39 JP6 1-2
40 on board Oscillator: 66M
41
Dave Liu66dc2c22007-06-25 13:21:12 +0800421.3 Since different board/chip rev. combinations have AC timing issues,
43 u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default
44 by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers).
45
46 When the rev2.x silicon mount on these boards, and if you are using
47 u-boot version after this patch, to make the ethernet interfaces usable,
48 and to enable RGMII-ID on your board, you have to setup the jumpers
49 correctly.
50
51 * MPC8360E-MDS-PB PROTO
52 nothing to do
53 * MPC8360E-MDS-PB PILOT
54 JP9 and JP8 should be ON
55 * MPC8360EA-MDS-PB PROTO
56 JP2 and JP3 should be ON
Dave Liuac4b5622006-10-31 19:54:59 -060057
582. Memory Map
59
602.1. The memory map should look pretty much like this:
61
62 0x0000_0000 0x7fff_ffff DDR 2G
63 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
64 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
65 0xc000_0000 0xdfff_ffff Empty 512M
66 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
67 0xe020_0000 0xe02f_ffff Empty 1M
68 0xe030_0000 0xe03f_ffff PCI IO 1M
69 0xe040_0000 0xefff_ffff Empty 252M
70 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M
71 0xf400_0000 0xf7ff_ffff Empty 64M
72 0xf800_0000 0xf800_7fff BCSR on CS1 32K
73 0xf800_8000 0xf800_ffff PIB CS4 32K
74 0xf801_0000 0xf801_7fff PIB CS5 32K
75 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
76
77
783. Definitions
79
803.1 Explanation of NEW definitions in:
81
82 include/configs/MPC8360EMDS.h
83
Peter Tyser0f898602009-05-22 17:23:24 -050084 CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
Dave Liuac4b5622006-10-31 19:54:59 -060085 CONFIG_MPC8360 MPC8360 specific
86 CONFIG_MPC8360EMDS MPC8360EMDS board specific
87
884. Compilation
89
Jerry Huang6be55ee2011-11-07 13:20:21 +080090 MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip).
91
Dave Liuac4b5622006-10-31 19:54:59 -060092 Assuming you're using BASH shell:
93
94 export CROSS_COMPILE=your-cross-compile-prefix
95 cd u-boot
96 make distclean
Jerry Huang6be55ee2011-11-07 13:20:21 +080097 make MPC8360EMDS_XX_config
Dave Liuac4b5622006-10-31 19:54:59 -060098 make
99
Jerry Huang6be55ee2011-11-07 13:20:21 +0800100 MPC8360EMDS support ATM, PCI in host and slave mode.
101
102 To make u-boot support ATM :
103 1) Make MPC8360EMDS_XX_ATM_config
Dave Liuac4b5622006-10-31 19:54:59 -0600104
105 To make u-boot support PCI host 66M :
106 1) DIP SW support PCI mode as described in Section 1.1.
Jerry Huang6be55ee2011-11-07 13:20:21 +0800107 2) Make MPC8360EMDS_XX_HOST_66_config
Dave Liuac4b5622006-10-31 19:54:59 -0600108
109 To make u-boot support PCI host 33M :
110 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
Jerry Huang6be55ee2011-11-07 13:20:21 +0800111 2) Make MPC8360EMDS_XX_HOST_33_config
Dave Liuac4b5622006-10-31 19:54:59 -0600112
113 To make u-boot support PCI slave 66M :
114 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
Jerry Huang6be55ee2011-11-07 13:20:21 +0800115 2) Make MPC8360EMDS_XX_SLAVE_config
Dave Liuac4b5622006-10-31 19:54:59 -0600116
Jerry Huang6be55ee2011-11-07 13:20:21 +0800117 (where XX is:
118 33 - 33.33MHz oscillator
119 66 - 66MHz oscillator)
Dave Liuac4b5622006-10-31 19:54:59 -0600120
1215. Downloading and Flashing Images
122
1235.0 Download over serial line using Kermit:
124
125 loadb
126 [Drop to kermit:
127 ^\c
128 send <u-boot-bin-image>
129 c
130 ]
131
132
133 Or via tftp:
134
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100135 tftp 10000 u-boot.bin
Dave Liuac4b5622006-10-31 19:54:59 -0600136
1375.1 Reflash U-boot Image using U-boot
138
139 tftp 20000 u-boot.bin
140 protect off fef00000 fef3ffff
141 erase fef00000 fef3ffff
142
143 cp.b 20000 fef00000 xxxx
144
145 or
146
147 cp.b 20000 fef00000 3ffff
148
149
150You have to supply the correct byte count with 'xxxx' from the TFTP result log.
151Maybe 3ffff will work too, that corresponds to the erased sectors.
152
153
1546. Notes
155 1) The console baudrate for MPC8360EMDS is 115200bps.