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Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05301/*
2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Based on davinci_dvevm.h. Original Copyrights follow:
5 *
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05309 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * Board
16 */
Ben Gardiner3d248d32010-10-14 17:26:29 -040017#define CONFIG_DRIVER_TI_EMAC
Lad, Prabhakar63777662012-06-24 21:35:23 +000018/* check if direct NOR boot config is used */
19#ifndef CONFIG_DIRECT_NOR_BOOT
Stefano Babicd73a8a12010-11-11 15:38:02 +010020#define CONFIG_USE_SPIFLASH
Lad, Prabhakar63777662012-06-24 21:35:23 +000021#endif
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053022
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -040023
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053024/*
25 * SoC Configuration
26 */
27#define CONFIG_MACH_DAVINCI_DA850_EVM
28#define CONFIG_ARM926EJS /* arm926ejs CPU core */
29#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
Christian Riesch52b0f872011-11-28 23:46:18 +000030#define CONFIG_SOC_DA850 /* TI DA850 SoC */
Christian Rieschb67d8812012-02-02 00:44:39 +000031#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053032#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
33#define CONFIG_SYS_OSCIN_FREQ 24000000
34#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
35#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Sughosh Ganu6b873dc2012-02-02 00:44:41 +000036#define CONFIG_SYS_DA850_PLL_INIT
37#define CONFIG_SYS_DA850_DDR_INIT
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053038
Lad, Prabhakar63777662012-06-24 21:35:23 +000039#ifdef CONFIG_DIRECT_NOR_BOOT
40#define CONFIG_ARCH_CPU_INIT
41#define CONFIG_DA8XX_GPIO
42#define CONFIG_SYS_TEXT_BASE 0x60000000
43#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
44#define CONFIG_DA850_LOWLEVEL
45#else
46#define CONFIG_SYS_TEXT_BASE 0xc1080000
47#endif
48
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053049/*
50 * Memory Info
51 */
52#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053053#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
54#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
Ben Gardiner97003752010-08-23 09:08:15 -040055#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053056
57/* memtest start addr */
58#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
59
60/* memtest will be run on 16MB */
61#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
62
63#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053064
Christian Riesch3d2c8e62011-12-09 09:47:37 +000065#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
66 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
67 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
68 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
69 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
70 DAVINCI_SYSCFG_SUSPSRC_I2C)
71
72/*
73 * PLL configuration
74 */
75#define CONFIG_SYS_DV_CLKMODE 0
76#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
77#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
78#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
79#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
80#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
81#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
82#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
83#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
84
85#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
86#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
87#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
88#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
89
90#define CONFIG_SYS_DA850_PLL0_PLLM 24
91#define CONFIG_SYS_DA850_PLL1_PLLM 21
92
93/*
94 * DDR2 memory configuration
95 */
96#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
97 DV_DDR_PHY_EXT_STRBEN | \
98 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
99
100#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
101 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
102 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
103 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
104 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
105 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
106 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
107 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
108
109/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
110#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
111
112#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
113 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
114 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
115 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
116 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
117 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
118 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
119 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
120 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
121
122#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
123 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
124 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
125 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
126 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
127 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
128 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
129 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
130
131#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
132#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
133
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530134/*
135 * Serial Driver info
136 */
137#define CONFIG_SYS_NS16550
138#define CONFIG_SYS_NS16550_SERIAL
139#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
140#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
141#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
142#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
143#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530144
Stefano Babicd73a8a12010-11-11 15:38:02 +0100145#define CONFIG_SPI
146#define CONFIG_SPI_FLASH
147#define CONFIG_SPI_FLASH_STMICRO
Manjunathappa, Prakash8cf47392011-09-03 22:19:56 -0400148#define CONFIG_SPI_FLASH_WINBOND
Tom Rinidf166cc2013-10-08 15:08:38 -0400149#define CONFIG_CMD_SF
Stefano Babicd73a8a12010-11-11 15:38:02 +0100150#define CONFIG_DAVINCI_SPI
151#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
152#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
153#define CONFIG_SF_DEFAULT_SPEED 30000000
154#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
155
Lad, Prabhakar42612102012-06-24 21:35:19 +0000156#ifdef CONFIG_USE_SPIFLASH
157#define CONFIG_SPL_SPI_SUPPORT
158#define CONFIG_SPL_SPI_FLASH_SUPPORT
159#define CONFIG_SPL_SPI_LOAD
160#define CONFIG_SPL_SPI_BUS 0
161#define CONFIG_SPL_SPI_CS 0
162#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
163#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
164#endif
165
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530166/*
167 * I2C Configuration
168 */
169#define CONFIG_HARD_I2C
170#define CONFIG_DRIVER_DAVINCI_I2C
171#define CONFIG_SYS_I2C_SPEED 25000
172#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500173#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530174
175/*
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400176 * Flash & Environment
177 */
178#ifdef CONFIG_USE_NAND
179#undef CONFIG_ENV_IS_IN_FLASH
180#define CONFIG_NAND_DAVINCI
181#define CONFIG_SYS_NO_FLASH
182#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
183#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
184#define CONFIG_ENV_SIZE (128 << 10)
185#define CONFIG_SYS_NAND_USE_FLASH_BBT
186#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
187#define CONFIG_SYS_NAND_PAGE_2K
188#define CONFIG_SYS_NAND_CS 3
189#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Eric Benard34fa0702013-04-22 05:55:00 +0000190#define CONFIG_SYS_NAND_MASK_CLE 0x10
191#define CONFIG_SYS_NAND_MASK_ALE 0x8
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400192#undef CONFIG_SYS_NAND_HW_ECC
193#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000194#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
195#define CONFIG_SYS_NAND_5_ADDR_CYCLE
196#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
197#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
198#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
199#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
200#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
201#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
202#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
203 CONFIG_SYS_NAND_U_BOOT_SIZE - \
204 CONFIG_SYS_MALLOC_LEN - \
205 GENERATED_GBL_DATA_SIZE)
206#define CONFIG_SYS_NAND_ECCPOS { \
207 24, 25, 26, 27, 28, \
208 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
209 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
210 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
211 59, 60, 61, 62, 63 }
212#define CONFIG_SYS_NAND_PAGE_COUNT 64
213#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
214#define CONFIG_SYS_NAND_ECCSIZE 512
215#define CONFIG_SYS_NAND_ECCBYTES 10
216#define CONFIG_SYS_NAND_OOBSIZE 64
217#define CONFIG_SPL_NAND_SUPPORT
Scott Wood6f2f01b2012-09-20 19:09:07 -0500218#define CONFIG_SPL_NAND_BASE
219#define CONFIG_SPL_NAND_DRIVERS
220#define CONFIG_SPL_NAND_ECC
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000221#define CONFIG_SPL_NAND_SIMPLE
222#define CONFIG_SPL_NAND_LOAD
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400223#endif
224
225/*
Ben Gardiner3d248d32010-10-14 17:26:29 -0400226 * Network & Ethernet Configuration
227 */
228#ifdef CONFIG_DRIVER_TI_EMAC
Ben Gardiner3d248d32010-10-14 17:26:29 -0400229#define CONFIG_MII
Ben Gardiner3d248d32010-10-14 17:26:29 -0400230#define CONFIG_BOOTP_DNS
231#define CONFIG_BOOTP_DNS2
232#define CONFIG_BOOTP_SEND_HOSTNAME
233#define CONFIG_NET_RETRY_COUNT 10
Ben Gardiner3d248d32010-10-14 17:26:29 -0400234#endif
235
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -0400236#ifdef CONFIG_USE_NOR
237#define CONFIG_ENV_IS_IN_FLASH
238#define CONFIG_FLASH_CFI_DRIVER
239#define CONFIG_SYS_FLASH_CFI
240#define CONFIG_SYS_FLASH_PROTECTION
241#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
242#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
243#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
244#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
245#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
246#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
247#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
248 + 3)
249#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
250#endif
251
Stefano Babicd73a8a12010-11-11 15:38:02 +0100252#ifdef CONFIG_USE_SPIFLASH
253#undef CONFIG_ENV_IS_IN_FLASH
254#undef CONFIG_ENV_IS_IN_NAND
255#define CONFIG_ENV_IS_IN_SPI_FLASH
256#define CONFIG_ENV_SIZE (64 << 10)
257#define CONFIG_ENV_OFFSET (256 << 10)
258#define CONFIG_ENV_SECT_SIZE (64 << 10)
259#define CONFIG_SYS_NO_FLASH
260#endif
261
Ben Gardiner3d248d32010-10-14 17:26:29 -0400262/*
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530263 * U-Boot general configuration
264 */
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400265#define CONFIG_MISC_INIT_R
Christian Rieschae5c77d2011-10-13 00:52:29 +0000266#define CONFIG_BOARD_EARLY_INIT_F
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530267#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Nagabhushana Netagunteac935e52011-09-03 22:18:59 -0400268#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530269#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
270#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
271#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
272#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
273#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
274#define CONFIG_VERSION_VARIABLE
275#define CONFIG_AUTO_COMPLETE
276#define CONFIG_SYS_HUSH_PARSER
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530277#define CONFIG_CMDLINE_EDITING
278#define CONFIG_SYS_LONGHELP
279#define CONFIG_CRC32_VERIFY
280#define CONFIG_MX_CYCLIC
281
282/*
283 * Linux Information
284 */
Ben Gardiner59e0d612010-10-14 17:26:32 -0400285#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400286#define CONFIG_HWCONFIG /* enable hwconfig */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530287#define CONFIG_CMDLINE_TAG
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500288#define CONFIG_REVISION_TAG
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530289#define CONFIG_SETUP_MEMORY_TAGS
290#define CONFIG_BOOTARGS \
291 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
292#define CONFIG_BOOTDELAY 3
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400293#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530294
295/*
296 * U-Boot commands
297 */
298#include <config_cmd_default.h>
299#define CONFIG_CMD_ENV
300#define CONFIG_CMD_ASKENV
301#define CONFIG_CMD_DHCP
302#define CONFIG_CMD_DIAG
303#define CONFIG_CMD_MII
304#define CONFIG_CMD_PING
305#define CONFIG_CMD_SAVES
306#define CONFIG_CMD_MEMORY
307
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000308#ifdef CONFIG_CMD_BDI
309#define CONFIG_CLOCKS
310#endif
311
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530312#ifndef CONFIG_DRIVER_TI_EMAC
313#undef CONFIG_CMD_NET
314#undef CONFIG_CMD_DHCP
315#undef CONFIG_CMD_MII
316#undef CONFIG_CMD_PING
317#endif
318
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400319#ifdef CONFIG_USE_NAND
320#undef CONFIG_CMD_FLASH
321#undef CONFIG_CMD_IMLS
322#define CONFIG_CMD_NAND
Ben Gardiner771d0282010-10-14 17:26:27 -0400323
324#define CONFIG_CMD_MTDPARTS
325#define CONFIG_MTD_DEVICE
326#define CONFIG_MTD_PARTITIONS
327#define CONFIG_LZO
328#define CONFIG_RBTREE
329#define CONFIG_CMD_UBI
330#define CONFIG_CMD_UBIFS
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400331#endif
332
Stefano Babicd73a8a12010-11-11 15:38:02 +0100333#ifdef CONFIG_USE_SPIFLASH
334#undef CONFIG_CMD_IMLS
335#undef CONFIG_CMD_FLASH
336#define CONFIG_CMD_SPI
Stefano Babicd73a8a12010-11-11 15:38:02 +0100337#define CONFIG_CMD_SAVEENV
338#endif
339
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530340#if !defined(CONFIG_USE_NAND) && \
341 !defined(CONFIG_USE_NOR) && \
342 !defined(CONFIG_USE_SPIFLASH)
343#define CONFIG_ENV_IS_NOWHERE
344#define CONFIG_SYS_NO_FLASH
345#define CONFIG_ENV_SIZE (16 << 10)
346#undef CONFIG_CMD_IMLS
347#undef CONFIG_CMD_ENV
348#endif
349
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000350/* SD/MMC configuration */
Rajashekhara, Sudhakar4a5edda2012-06-24 21:35:17 +0000351#ifndef CONFIG_USE_NOR
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000352#define CONFIG_MMC
353#define CONFIG_DAVINCI_MMC_SD1
354#define CONFIG_GENERIC_MMC
355#define CONFIG_DAVINCI_MMC
Rajashekhara, Sudhakar4a5edda2012-06-24 21:35:17 +0000356#endif
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000357
358/*
359 * Enable MMC commands only when
360 * MMC support is present
361 */
362#ifdef CONFIG_MMC
363#define CONFIG_DOS_PARTITION
364#define CONFIG_CMD_EXT2
365#define CONFIG_CMD_FAT
366#define CONFIG_CMD_MMC
367#endif
368
Lad, Prabhakar63777662012-06-24 21:35:23 +0000369#ifndef CONFIG_DIRECT_NOR_BOOT
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000370/* defines for SPL */
371#define CONFIG_SPL
Tom Rini3f7f2412012-08-14 12:27:13 -0700372#define CONFIG_SPL_FRAMEWORK
373#define CONFIG_SPL_BOARD_INIT
374#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
375 CONFIG_SYS_MALLOC_LEN)
376#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
377#define CONFIG_SPL_SPI_SUPPORT
378#define CONFIG_SPL_SPI_FLASH_SUPPORT
379#define CONFIG_SPL_SPI_LOAD
380#define CONFIG_SPL_SPI_BUS 0
381#define CONFIG_SPL_SPI_CS 0
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000382#define CONFIG_SPL_SERIAL_SUPPORT
383#define CONFIG_SPL_LIBCOMMON_SUPPORT
384#define CONFIG_SPL_LIBGENERIC_SUPPORT
Sughosh Ganu6b873dc2012-02-02 00:44:41 +0000385#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000386#define CONFIG_SPL_STACK 0x8001ff00
387#define CONFIG_SPL_TEXT_BASE 0x80000000
Albert ARIBAUDb7b5f1a2013-04-12 05:14:32 +0000388#define CONFIG_SPL_MAX_FOOTPRINT 32768
Lad, Prabhakar63777662012-06-24 21:35:23 +0000389#endif
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000390
391/* Load U-Boot Image From MMC */
392#ifdef CONFIG_SPL_MMC_LOAD
393#define CONFIG_SPL_MMC_SUPPORT
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000394#define CONFIG_SPL_LIBDISK_SUPPORT
Tom Rini3f7f2412012-08-14 12:27:13 -0700395#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75
396#undef CONFIG_SPL_SPI_SUPPORT
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000397#undef CONFIG_SPL_SPI_LOAD
398#endif
399
Heiko Schocherab86f722010-09-17 13:10:42 +0200400/* additions for new relocation code, must added to all boards */
Heiko Schocherab86f722010-09-17 13:10:42 +0200401#define CONFIG_SYS_SDRAM_BASE 0xc0000000
Lad, Prabhakar63777662012-06-24 21:35:23 +0000402
403#ifdef CONFIG_DIRECT_NOR_BOOT
404#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
405#else
Heiko Schocherab86f722010-09-17 13:10:42 +0200406#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200407 GENERATED_GBL_DATA_SIZE)
Lad, Prabhakar63777662012-06-24 21:35:23 +0000408#endif /* CONFIG_DIRECT_NOR_BOOT */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530409#endif /* __CONFIG_H */