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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * (C) Copyright 2002
6 * Gregory E. Allen, gallen@arlut.utexas.edu
7 * Matthew E. Karger, karger@arlut.utexas.edu
8 * Applied Research Laboratories, The University of Texas at Austin
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +000011 */
12
13#include <common.h>
14#include <mpc824x.h>
15#include <asm/processor.h>
16#include <asm/io.h>
wdenk7a8e9bed2003-05-31 18:35:21 +000017#include <asm/mmu.h>
wdenkc6097192002-11-03 00:24:07 +000018#include <pci.h>
Ben Warren10efa022008-08-31 20:37:00 -070019#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +000020
21#define SAVE_SZ 32
22
23
24int checkboard(void)
25{
26 ulong busfreq = get_bus_freq(0);
27 char buf[32];
28
29 printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq));
30 return 0;
31}
32
33
Becky Bruce9973e3c2008-06-09 16:03:40 -050034phys_size_t initdram(int board_type)
wdenkc6097192002-11-03 00:24:07 +000035{
wdenkc83bf6a2004-01-06 22:38:14 +000036 long size;
37 long new_bank0_end;
wdenk498b8db2004-04-18 22:26:17 +000038 long new_bank1_end;
wdenkc83bf6a2004-01-06 22:38:14 +000039 long mear1;
40 long emear1;
wdenkc6097192002-11-03 00:24:07 +000041
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
wdenkc6097192002-11-03 00:24:07 +000043
wdenk498b8db2004-04-18 22:26:17 +000044 new_bank0_end = size/2 - 1;
45 new_bank1_end = size - 1;
wdenkc83bf6a2004-01-06 22:38:14 +000046 mear1 = mpc824x_mpc107_getreg(MEAR1);
47 emear1 = mpc824x_mpc107_getreg(EMEAR1);
wdenk498b8db2004-04-18 22:26:17 +000048
49 mear1 = (mear1 & 0xFFFF0000) |
50 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
51 ((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8);
52 emear1 = (emear1 & 0xFFFF0000) |
53 ((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
54 ((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8);
wdenke35745b2004-04-18 23:32:11 +000055
wdenkc83bf6a2004-01-06 22:38:14 +000056 mpc824x_mpc107_setreg(MEAR1, mear1);
57 mpc824x_mpc107_setreg(EMEAR1, emear1);
wdenkc6097192002-11-03 00:24:07 +000058
wdenkc83bf6a2004-01-06 22:38:14 +000059 return (size);
wdenkc6097192002-11-03 00:24:07 +000060}
61
62
63/*
64 * Initialize PCI Devices, report devices found.
65 */
66
67static struct pci_config_table pci_utx8245_config_table[] = {
68#ifndef CONFIG_PCI_PNP
wdenk7a8e9bed2003-05-31 18:35:21 +000069 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID,
wdenkc6097192002-11-03 00:24:07 +000070 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
71 PCI_ENET0_MEMADDR,
72 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
wdenk7a8e9bed2003-05-31 18:35:21 +000073 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID,
wdenkc6097192002-11-03 00:24:07 +000074 pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR,
75 PCI_FIREWIRE_MEMADDR,
76 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
77#endif /*CONFIG_PCI_PNP*/
78 { }
79};
80
81
82static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
83{
84 if (PCI_DEV(dev) == 11)
85 /* assign serial interrupt line 9 (int25) to FireWire */
86 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25);
87
88 else if (PCI_DEV(dev) == 12)
89 /* assign serial interrupt line 8 (int24) to Ethernet */
90 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24);
wdenk7a8e9bed2003-05-31 18:35:21 +000091
92 else if (PCI_DEV(dev) == 14)
93 /* assign serial interrupt line 0 (int16) to PMC slot 0 */
94 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16);
95
96 else if (PCI_DEV(dev) == 15)
97 /* assign serial interrupt line 1 (int17) to PMC slot 1 */
98 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17);
wdenkc6097192002-11-03 00:24:07 +000099}
100
101static struct pci_controller utx8245_hose = {
102#ifndef CONFIG_PCI_PNP
103 config_table: pci_utx8245_config_table,
104 fixup_irq: pci_utx8245_fixup_irq,
105 write_byte: pci_hose_write_config_byte
106#endif /*CONFIG_PCI_PNP*/
107};
108
stroesead10dd92003-02-14 11:21:23 +0000109void pci_init_board (void)
wdenkc6097192002-11-03 00:24:07 +0000110{
111 pci_mpc824x_init(&utx8245_hose);
112
113 icache_enable();
114}
Ben Warren10efa022008-08-31 20:37:00 -0700115
116int board_eth_init(bd_t *bis)
117{
118 return pci_eth_init(bis);
119}