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Stefan Roese8a316c92005-08-01 16:49:12 +02001/*
2 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * bamboo.h - configuration for BAMBOO board
26 ***********************************************************************/
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
Stefan Roese17f50f222005-08-04 17:09:16 +020033#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
Stefan Roese846b0dd2005-08-08 12:42:22 +020034#define CONFIG_440EP 1 /* Specific PPC440EP support */
Stefan Roese17f50f222005-08-04 17:09:16 +020035#define CONFIG_4xx 1 /* ... PPC4xx family */
Stefan Roese8a316c92005-08-01 16:49:12 +020036#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
37
Stefan Roesec57c7982005-08-11 17:56:56 +020038#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
39
40/*
41 * Please note that, if NAND support is enabled, the 2nd ethernet port
42 * can't be used because of pin multiplexing. So, if you want to use the
43 * 2nd ethernet port you have to "undef" the following define.
44 */
45#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
46
Stefan Roese8a316c92005-08-01 16:49:12 +020047/*-----------------------------------------------------------------------
48 * Base addresses -- Note these are effective addresses where the
49 * actual resources get mapped (not physical addresses)
50 *----------------------------------------------------------------------*/
Stefan Roese17f50f222005-08-04 17:09:16 +020051#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
52#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
53#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
54#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
55#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
56#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
57#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
58#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
59#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
Stefan Roese8a316c92005-08-01 16:49:12 +020060
61/*Don't change either of these*/
Stefan Roese17f50f222005-08-04 17:09:16 +020062#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
63#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
Stefan Roese8a316c92005-08-01 16:49:12 +020064/*Don't change either of these*/
65
Stefan Roese17f50f222005-08-04 17:09:16 +020066#define CFG_USB_DEVICE 0x50000000
67#define CFG_NVRAM_BASE_ADDR 0x80000000
Stefan Roesec57c7982005-08-11 17:56:56 +020068#define CFG_BOOT_BASE_ADDR 0xf0000000
69#define CFG_NAND_ADDR 0x90000000
70#define CFG_NAND2_ADDR 0x94000000
Stefan Roese8a316c92005-08-01 16:49:12 +020071
72/*-----------------------------------------------------------------------
73 * Initial RAM & stack pointer (placed in SDRAM)
74 *----------------------------------------------------------------------*/
Stefan Roesec57c7982005-08-11 17:56:56 +020075#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
76#define CFG_INIT_RAM_END (8 << 10)
Stefan Roese17f50f222005-08-04 17:09:16 +020077#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
Stefan Roese8a316c92005-08-01 16:49:12 +020078#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
79#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
80
Stefan Roese8a316c92005-08-01 16:49:12 +020081/*-----------------------------------------------------------------------
82 * Serial Port
83 *----------------------------------------------------------------------*/
84#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
Wolfgang Denk095b8a32005-08-02 17:06:17 +020085#define CONFIG_BAUDRATE 115200
Stefan Roese17f50f222005-08-04 17:09:16 +020086#define CONFIG_SERIAL_MULTI 1
87/* define this if you want console on UART1 */
Stefan Roese8a316c92005-08-01 16:49:12 +020088#undef CONFIG_UART1_CONSOLE
89
90#define CFG_BAUDRATE_TABLE \
91 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
92
93/*-----------------------------------------------------------------------
94 * NVRAM/RTC
95 *
96 * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
97 * The DS1558 code assumes this condition
98 *
99 *----------------------------------------------------------------------*/
Stefan Roesec57c7982005-08-11 17:56:56 +0200100#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
Stefan Roese17f50f222005-08-04 17:09:16 +0200101#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
102
103/*-----------------------------------------------------------------------
104 * Environment
105 *----------------------------------------------------------------------*/
106/*
107 * Define here the location of the environment variables (FLASH or EEPROM).
108 * Note: DENX encourages to use redundant environment in FLASH.
109 */
110#if 1
111#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
112#else
113#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
114#endif
Stefan Roese8a316c92005-08-01 16:49:12 +0200115
116/*-----------------------------------------------------------------------
117 * FLASH related
118 *----------------------------------------------------------------------*/
Stefan Roese17f50f222005-08-04 17:09:16 +0200119#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
Stefan Roese8a316c92005-08-01 16:49:12 +0200120#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
121
122#undef CFG_FLASH_CHECKSUM
123#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
Stefan Roese8a316c92005-08-01 16:49:12 +0200124#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
125
Stefan Roese17f50f222005-08-04 17:09:16 +0200126#define CFG_FLASH_ADDR0 0x555
127#define CFG_FLASH_ADDR1 0x2aa
128#define CFG_FLASH_WORD_SIZE unsigned char
129
Stefan Roesec57c7982005-08-11 17:56:56 +0200130#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
131#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
Stefan Roese17f50f222005-08-04 17:09:16 +0200132
133#ifdef CFG_ENV_IS_IN_FLASH
134#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
135#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
Stefan Roesec57c7982005-08-11 17:56:56 +0200136#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese17f50f222005-08-04 17:09:16 +0200137
Stefan Roese17f50f222005-08-04 17:09:16 +0200138/* Address and size of Redundant Environment Sector */
139#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
140#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
Stefan Roese17f50f222005-08-04 17:09:16 +0200141#endif /* CFG_ENV_IS_IN_FLASH */
Stefan Roese8a316c92005-08-01 16:49:12 +0200142
143/*-----------------------------------------------------------------------
Stefan Roesec57c7982005-08-11 17:56:56 +0200144 * NAND-FLASH related
145 *----------------------------------------------------------------------*/
146#define NAND_CMD_REG (0x00) /* NandFlash Command Register */
147#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */
148#define NAND_DATA_REG (0x08) /* NandFlash Data Register */
149#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */
150#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */
151#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */
152#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */
153#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */
154#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */
155#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */
156#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */
157#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */
158#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */
159#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */
160#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */
161#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */
162#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */
163#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
164#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
165
166/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
167#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */
168#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */
169#define NAND0_CMD_READ2 0x50
170#define NAND0_CMD_READ_ID 0x90
171#define NAND0_CMD_READ_STATUS 0x70
172#define NAND0_CMD_RESET 0xFF
173#define NAND0_CMD_PAGE_PROG 0x80
174#define NAND0_CMD_PAGE_PROG_TRUE 0x10
175#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
176#define NAND0_CMD_BLOCK_ERASE 0x60
177#define NAND0_CMD_BLOCK_ERASE_END 0xD0
178
179#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
180#define SECTORSIZE 512
181
182#define ADDR_COLUMN 1
183#define ADDR_PAGE 2
184#define ADDR_COLUMN_PAGE 3
185
186#define NAND_ChipID_UNKNOWN 0x00
187#define NAND_MAX_FLOORS 1
188#define NAND_MAX_CHIPS 1
189
190#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
191#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
192#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
193#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
194#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
195
196/* not needed with 440EP NAND controller */
197#define NAND_CTL_CLRALE(nandptr)
198#define NAND_CTL_SETALE(nandptr)
199#define NAND_CTL_CLRCLE(nandptr)
200#define NAND_CTL_SETCLE(nandptr)
201#define NAND_DISABLE_CE(nand)
202#define NAND_ENABLE_CE(nand)
203
204/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +0200205 * DDR SDRAM
Stefan Roese17f50f222005-08-04 17:09:16 +0200206 *----------------------------------------------------------------------------- */
207#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
208#define SPD_EEPROM_ADDRESS {0x50,0x51} /* SPD i2c spd addresses */
209#define CFG_SDRAM_ONBOARD_SIZE (64 << 20) /* Bamboo has onboard and DIMM-slots!*/
Stefan Roese8a316c92005-08-01 16:49:12 +0200210
211/*-----------------------------------------------------------------------
212 * I2C
213 *----------------------------------------------------------------------*/
214#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
215#undef CONFIG_SOFT_I2C /* I2C bit-banged */
216#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
217#define CFG_I2C_SLAVE 0x7F
218
Stefan Roese8a316c92005-08-01 16:49:12 +0200219#define CFG_I2C_MULTI_EEPROMS
Stefan Roese8a316c92005-08-01 16:49:12 +0200220#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
221#define CFG_I2C_EEPROM_ADDR_LEN 1
222#define CFG_EEPROM_PAGE_WRITE_ENABLE
223#define CFG_EEPROM_PAGE_WRITE_BITS 3
224#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
225
Stefan Roese17f50f222005-08-04 17:09:16 +0200226#ifdef CFG_ENV_IS_IN_EEPROM
227#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
228#define CFG_ENV_OFFSET 0x0
229#endif /* CFG_ENV_IS_IN_EEPROM */
230
231#define CONFIG_PREBOOT "echo;" \
232 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
233 "echo"
234
235#undef CONFIG_BOOTARGS
236
237#define CONFIG_EXTRA_ENV_SETTINGS \
238 "netdev=eth0\0" \
239 "hostname=bamboo\0" \
240 "nfsargs=setenv bootargs root=/dev/nfs rw " \
241 "nfsroot=$(serverip):$(rootpath)\0" \
242 "ramargs=setenv bootargs root=/dev/ram rw\0" \
243 "addip=setenv bootargs $(bootargs) " \
244 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
245 ":$(hostname):$(netdev):off panic=1\0" \
246 "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
247 "flash_nfs=run nfsargs addip addtty;" \
248 "bootm $(kernel_addr)\0" \
249 "flash_self=run ramargs addip addtty;" \
250 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
251 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
252 "bootm\0" \
253 "rootpath=/opt/eldk/ppc_4xx\0" \
254 "bootfile=/tftpboot/bamboo/uImage\0" \
255 "kernel_addr=fff00000\0" \
256 "ramdisk_addr=fff10000\0" \
257 "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
258 "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
259 "cp.b 100000 fff80000 80000;" \
260 "setenv filesize;saveenv\0" \
261 "upd=run load;run update\0" \
262 ""
263#define CONFIG_BOOTCOMMAND "run flash_self"
264
265#if 0
266#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
267#else
268#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
269#endif
270
271#define CONFIG_BAUDRATE 115200
Stefan Roese8a316c92005-08-01 16:49:12 +0200272
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200273#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Stefan Roese8a316c92005-08-01 16:49:12 +0200274#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
275
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200276#define CONFIG_MII 1 /* MII PHY management */
Stefan Roese17f50f222005-08-04 17:09:16 +0200277#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200278#define CONFIG_PHY1_ADDR 1
Stefan Roesec57c7982005-08-11 17:56:56 +0200279
280#ifndef CONFIG_BAMBOO_NAND
281#define CONFIG_NET_MULTI 1 /* required for netconsole */
Stefan Roese8a316c92005-08-01 16:49:12 +0200282#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
Stefan Roesec57c7982005-08-11 17:56:56 +0200283#endif /* CONFIG_BAMBOO_NAND */
284
Stefan Roese17f50f222005-08-04 17:09:16 +0200285#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Stefan Roese8a316c92005-08-01 16:49:12 +0200286
287/* Partitions */
288#define CONFIG_MAC_PARTITION
289#define CONFIG_DOS_PARTITION
290#define CONFIG_ISO_PARTITION
291
Stefan Roese846b0dd2005-08-08 12:42:22 +0200292#ifdef CONFIG_440EP
Stefan Roese8a316c92005-08-01 16:49:12 +0200293/* USB */
294#define CONFIG_USB_OHCI
295#define CONFIG_USB_STORAGE
296
297/*Comment this out to enable USB 1.1 device*/
298#define USB_2_0_DEVICE
Stefan Roese846b0dd2005-08-08 12:42:22 +0200299#endif /*CONFIG_440EP*/
Stefan Roese8a316c92005-08-01 16:49:12 +0200300
Stefan Roesec57c7982005-08-11 17:56:56 +0200301#ifdef CONFIG_BAMBOO_NAND
302#define _CFG_CMD_NAND CFG_CMD_NAND
303#else
304#define _CFG_CMD_NAND 0
305#endif /* CONFIG_BAMBOO_NAND */
306
Stefan Roese17f50f222005-08-04 17:09:16 +0200307#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
308 CFG_CMD_ASKENV | \
Stefan Roesec57c7982005-08-11 17:56:56 +0200309 CFG_CMD_EEPROM | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200310 CFG_CMD_DATE | \
311 CFG_CMD_DHCP | \
312 CFG_CMD_DIAG | \
313 CFG_CMD_ELF | \
314 CFG_CMD_I2C | \
315 CFG_CMD_IRQ | \
316 CFG_CMD_MII | \
317 CFG_CMD_NET | \
318 CFG_CMD_NFS | \
319 CFG_CMD_PCI | \
320 CFG_CMD_PING | \
321 CFG_CMD_REGINFO | \
322 CFG_CMD_SDRAM | \
323 CFG_CMD_USB | \
Stefan Roesec57c7982005-08-11 17:56:56 +0200324 _CFG_CMD_NAND | \
Stefan Roese17f50f222005-08-04 17:09:16 +0200325 CFG_CMD_SNTP )
Stefan Roese8a316c92005-08-01 16:49:12 +0200326
327/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
328#include <cmd_confdefs.h>
329
330/*
331 * Miscellaneous configurable options
332 */
333#define CFG_LONGHELP /* undef to save memory */
Stefan Roesec57c7982005-08-11 17:56:56 +0200334#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Stefan Roese8a316c92005-08-01 16:49:12 +0200335#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
Stefan Roesec57c7982005-08-11 17:56:56 +0200336#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese8a316c92005-08-01 16:49:12 +0200337#else
Stefan Roesec57c7982005-08-11 17:56:56 +0200338#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese8a316c92005-08-01 16:49:12 +0200339#endif
Stefan Roesec57c7982005-08-11 17:56:56 +0200340#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
341#define CFG_MAXARGS 16 /* max number of command args */
342#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese8a316c92005-08-01 16:49:12 +0200343
Stefan Roesec57c7982005-08-11 17:56:56 +0200344#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
345#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese8a316c92005-08-01 16:49:12 +0200346
347#define CFG_LOAD_ADDR 0x100000 /* default load address */
Stefan Roesec57c7982005-08-11 17:56:56 +0200348#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
349#define CONFIG_LYNXKDI 1 /* support kdi files */
Stefan Roese8a316c92005-08-01 16:49:12 +0200350
Stefan Roesec57c7982005-08-11 17:56:56 +0200351#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese8a316c92005-08-01 16:49:12 +0200352
353/*-----------------------------------------------------------------------
354 * PCI stuff
355 *-----------------------------------------------------------------------
356 */
357/* General PCI */
Stefan Roesec57c7982005-08-11 17:56:56 +0200358#define CONFIG_PCI /* include pci support */
359#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
Stefan Roese17f50f222005-08-04 17:09:16 +0200360#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Stefan Roesec57c7982005-08-11 17:56:56 +0200361#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
Stefan Roese8a316c92005-08-01 16:49:12 +0200362
363/* Board-specific PCI */
Stefan Roese17f50f222005-08-04 17:09:16 +0200364#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
Stefan Roese8a316c92005-08-01 16:49:12 +0200365#define CFG_PCI_TARGET_INIT
366#define CFG_PCI_MASTER_INIT
367
Stefan Roesec57c7982005-08-11 17:56:56 +0200368#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
369#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
Stefan Roese8a316c92005-08-01 16:49:12 +0200370
371/*
372 * For booting Linux, the board info and command line data
373 * have to be in the first 8 MB of memory, since this is
374 * the maximum mapped by the Linux kernel during initialization.
375 */
376#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese17f50f222005-08-04 17:09:16 +0200377
Stefan Roese8a316c92005-08-01 16:49:12 +0200378/*-----------------------------------------------------------------------
379 * Cache Configuration
380 */
Stefan Roesec57c7982005-08-11 17:56:56 +0200381#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
Stefan Roese8a316c92005-08-01 16:49:12 +0200382#define CFG_CACHELINE_SIZE 32 /* ... */
383#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
384#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
385#endif
386
387/*
388 * Internal Definitions
389 *
390 * Boot Flags
391 */
392#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
393#define BOOTFLAG_WARM 0x02 /* Software reboot */
394
395#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
396#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
397#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
398#endif
399#endif /* __CONFIG_H */