blob: 87c73457a0ae7eba8e576be10ea91a2b6759ac7d [file] [log] [blame]
Ley Foon Tan380477f2019-11-27 15:55:31 +08001/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
4 *
5 */
6
7#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
8#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
9
10#include <asm/arch/base_addr_s10.h>
11#include <asm/arch/handoff_s10.h>
12
13/*
14 * U-Boot general configurations
15 */
16#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
17#define CONFIG_LOADADDR 0x2000000
18#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
19#define CONFIG_REMAKE_ELF
20/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
21#define CPU_RELEASE_ADDR 0xFFD12210
22#define CONFIG_SYS_CACHELINE_SIZE 64
23#define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */
24
25/*
26 * U-Boot console configurations
27 */
28#define CONFIG_SYS_MAXARGS 64
29#define CONFIG_SYS_CBSIZE 2048
30#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
31 sizeof(CONFIG_SYS_PROMPT) + 16)
32#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
33
34/* Extend size of kernel image for uncompression */
35#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
36
37/*
38 * U-Boot run time memory configurations
39 */
40#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
41#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
42#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
43 + CONFIG_SYS_INIT_RAM_SIZE \
44 - S10_HANDOFF_SIZE)
45#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
46#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
47
48/*
49 * U-Boot environment configurations
50 */
51#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
52
53/*
54 * QSPI support
55 */
56 #ifdef CONFIG_CADENCE_QSPI
57/* Enable it if you want to use dual-stacked mode */
58/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
59
60/* Flash device info */
61
62/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
63
64#ifndef CONFIG_SPL_BUILD
Ley Foon Tan380477f2019-11-27 15:55:31 +080065#define CONFIG_MTD_PARTITIONS
66#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
67#endif /* CONFIG_SPL_BUILD */
68
69#ifndef __ASSEMBLY__
70unsigned int cm_get_qspi_controller_clk_hz(void);
71#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
72#endif
73
74#endif /* CONFIG_CADENCE_QSPI */
75
76/*
77 * Boot arguments passed to the boot command. The value of
78 * CONFIG_BOOTARGS goes into the environment value "bootargs".
79 * Do note the value will override also the chosen node in FDT blob.
80 */
81#define CONFIG_BOOTARGS "earlycon"
82#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
83 "run mmcboot"
84
85#define CONFIG_EXTRA_ENV_SETTINGS \
86 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
87 "bootfile=Image\0" \
88 "fdt_addr=8000000\0" \
Ley Foon Tana76b7112019-11-27 15:55:32 +080089 "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
Ley Foon Tan380477f2019-11-27 15:55:31 +080090 "mmcroot=/dev/mmcblk0p2\0" \
91 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
92 " root=${mmcroot} rw rootwait;" \
93 "booti ${loadaddr} - ${fdt_addr}\0" \
94 "mmcload=mmc rescan;" \
95 "load mmc 0:1 ${loadaddr} ${bootfile};" \
96 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
97 "linux_qspi_enable=if sf probe; then " \
98 "echo Enabling QSPI at Linux DTB...;" \
99 "fdt addr ${fdt_addr}; fdt resize;" \
100 "fdt set /soc/spi@ff8d2000 status okay;" \
101 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
102 " ${qspi_clock}; fi; \0" \
103 "scriptaddr=0x02100000\0" \
104 "scriptfile=u-boot.scr\0" \
105 "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
106 "then source ${scriptaddr}; fi\0" \
107 "socfpga_legacy_reset_compat=1\0"
108
109/*
110 * Generic Interrupt Controller Definitions
111 */
112#define CONFIG_GICV2
113
114/*
115 * External memory configurations
116 */
117#define PHYS_SDRAM_1 0x0
118#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
119#define CONFIG_SYS_SDRAM_BASE 0
120#define CONFIG_SYS_MEMTEST_START 0
121#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000
122
123/*
124 * Serial / UART configurations
125 */
126#define CONFIG_SYS_NS16550_CLK 100000000
127#define CONFIG_SYS_NS16550_MEM32
128
129/*
130 * Timer & watchdog configurations
131 */
132#define COUNTER_FREQUENCY 400000000
133
134/*
135 * SDMMC configurations
136 */
137#ifdef CONFIG_CMD_MMC
138#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
139#endif
140/*
141 * Flash configurations
142 */
143#define CONFIG_SYS_MAX_FLASH_BANKS 1
144
145/* Ethernet on SoC (EMAC) */
146#if defined(CONFIG_CMD_NET)
147#define CONFIG_DW_ALTDESCRIPTOR
148#endif /* CONFIG_CMD_NET */
149
150/*
151 * L4 Watchdog
152 */
Marek Vasutcf8c8362019-06-27 01:19:23 +0200153#ifndef CONFIG_SPL_BUILD
Marek Vasut8941f842019-06-27 00:26:34 +0200154#undef CONFIG_HW_WATCHDOG
155#undef CONFIG_DESIGNWARE_WATCHDOG
156#endif
Ley Foon Tan380477f2019-11-27 15:55:31 +0800157#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
Ley Foon Tana76b7112019-11-27 15:55:32 +0800158#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
Ley Foon Tan380477f2019-11-27 15:55:31 +0800159#ifndef __ASSEMBLY__
160unsigned int cm_get_l4_sys_free_clk_hz(void);
161#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
162#endif
Ley Foon Tana76b7112019-11-27 15:55:32 +0800163#else
164#define CONFIG_DW_WDT_CLOCK_KHZ 100000
165#endif
Ley Foon Tan380477f2019-11-27 15:55:31 +0800166
167/*
168 * SPL memory layout
169 *
170 * On chip RAM
171 * 0xFFE0_0000 ...... Start of OCRAM
172 * SPL code, rwdata
173 * empty space
174 * 0xFFEx_xxxx ...... Top of stack (grows down)
175 * 0xFFEy_yyyy ...... Global Data
176 * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
177 * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
178 * 0xFFE3_FFFF ...... End of OCRAM
179 *
180 * SDRAM
181 * 0x0000_0000 ...... Start of SDRAM_1
182 * unused / empty space for image loading
183 * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
184 * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
185 * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
186 *
187 */
188#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
189#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
190#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
191#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
192#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
193 - CONFIG_SPL_BSS_MAX_SIZE)
194#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
195#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
196 - CONFIG_SYS_SPL_MALLOC_SIZE)
197
198/* SPL SDMMC boot support */
199#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
200#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
201
202#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */