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Jin Zhengxiong4782ac82006-08-23 19:10:44 +08001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08003 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jin Zhengxiong4782ac82006-08-23 19:10:44 +08007 */
8#ifndef _AHCI_H_
9#define _AHCI_H_
10
Rob Herring942e3142011-07-06 16:13:36 +000011#include <pci.h>
12
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080013#define AHCI_PCI_BAR 0x24
14#define AHCI_MAX_SG 56 /* hardware max is 64K */
15#define AHCI_CMD_SLOT_SZ 32
Stefano Babic9f472e62012-02-22 00:24:39 +000016#define AHCI_MAX_CMD_SLOT 32
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080017#define AHCI_RX_FIS_SZ 256
18#define AHCI_CMD_TBL_HDR 0x80
19#define AHCI_CMD_TBL_CDB 0x40
20#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
Stefano Babic9f472e62012-02-22 00:24:39 +000021#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
22 AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080023#define AHCI_CMD_ATAPI (1 << 5)
24#define AHCI_CMD_WRITE (1 << 6)
25#define AHCI_CMD_PREFETCH (1 << 7)
26#define AHCI_CMD_RESET (1 << 8)
27#define AHCI_CMD_CLR_BUSY (1 << 10)
28
29#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
30
31/* Global controller registers */
32#define HOST_CAP 0x00 /* host capabilities */
33#define HOST_CTL 0x04 /* global host control */
34#define HOST_IRQ_STAT 0x08 /* interrupt status */
35#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
36#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
Stefan Reinauer4e422bc2012-10-29 05:23:51 +000037#define HOST_CAP2 0x24 /* host capabilities, extended */
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080038
39/* HOST_CTL bits */
40#define HOST_RESET (1 << 0) /* reset controller; self-clear */
41#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
42#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
43
44/* Registers for each SATA port */
45#define PORT_LST_ADDR 0x00 /* command list DMA addr */
46#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
47#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
48#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
49#define PORT_IRQ_STAT 0x10 /* interrupt status */
50#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
51#define PORT_CMD 0x18 /* port command */
52#define PORT_TFDATA 0x20 /* taskfile data */
53#define PORT_SIG 0x24 /* device TF signature */
54#define PORT_CMD_ISSUE 0x38 /* command issue */
55#define PORT_SCR 0x28 /* SATA phy register block */
56#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
57#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
58#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
59#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
60
61/* PORT_IRQ_{STAT,MASK} bits */
62#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
63#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
64#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
65#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
66#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
67#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
68#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
69#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
70
71#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
72#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
73#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
74#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
75#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
76#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
77#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
78#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
79#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
80
Wolfgang Denk53677ef2008-05-20 16:00:29 +020081#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080082 | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
83
Wolfgang Denk53677ef2008-05-20 16:00:29 +020084#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
85 | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
86 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080087 | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
88 | PORT_IRQ_D2H_REG_FIS
89
Rob Herring2bdb10d2013-08-24 10:10:50 -050090/* PORT_SCR_STAT bits */
91#define PORT_SCR_STAT_DET_MASK 0x3
92#define PORT_SCR_STAT_DET_COMINIT 0x1
93#define PORT_SCR_STAT_DET_PHYRDY 0x3
94
Jin Zhengxiong4782ac82006-08-23 19:10:44 +080095/* PORT_CMD bits */
96#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
97#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
98#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
99#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
100#define PORT_CMD_CLO (1 << 3) /* Command list override */
101#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
102#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
103#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
104
105#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
106#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
107#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
108
109#define AHCI_MAX_PORTS 32
110
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800111#define ATA_FLAG_SATA (1 << 3)
112#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
113#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
114#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
115#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
116#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
117
118struct ahci_cmd_hdr {
119 u32 opts;
120 u32 status;
121 u32 tbl_addr;
122 u32 tbl_addr_hi;
123 u32 reserved[4];
124};
125
126struct ahci_sg {
127 u32 addr;
128 u32 addr_hi;
129 u32 reserved;
130 u32 flags_size;
131};
132
133struct ahci_ioports {
134 u32 cmd_addr;
135 u32 scr_addr;
136 u32 port_mmio;
137 struct ahci_cmd_hdr *cmd_slot;
138 struct ahci_sg *cmd_tbl_sg;
139 u32 cmd_tbl;
140 u32 rx_fis;
141};
142
143struct ahci_probe_ent {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200144 pci_dev_t dev;
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800145 struct ahci_ioports port[AHCI_MAX_PORTS];
146 u32 n_ports;
147 u32 hard_port_no;
148 u32 host_flags;
149 u32 host_set_flags;
150 u32 mmio_base;
151 u32 pio_mask;
152 u32 udma_mask;
153 u32 flags;
154 u32 cap; /* cache of HOST_CAP register */
155 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
156 u32 link_port_map; /*linkup port map*/
157};
158
Rob Herring942e3142011-07-06 16:13:36 +0000159int ahci_init(u32 base);
160
Jin Zhengxiong4782ac82006-08-23 19:10:44 +0800161#endif