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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -08002/*
3 * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
4 * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -08005 */
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +01006#include <clk.h>
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -08007#include <common.h>
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +01008#include <dm.h>
Simon Glass691d7192020-05-10 11:40:02 -06009#include <init.h>
Simon Glass336d4612020-02-03 07:36:16 -070010#include <malloc.h>
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080011#include <asm/arch/clk.h>
12
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080013DECLARE_GLOBAL_DATA_PTR;
14
Stefan Herbrechtsmeiere18c0f62017-01-17 16:27:27 +010015static const char * const clk_names[clk_max] = {
16 "armpll", "ddrpll", "iopll",
17 "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
18 "ddr2x", "ddr3x", "dci",
19 "lqspi", "smc", "pcap", "gem0", "gem1",
20 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
21 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
22 "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
23 "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
24 "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
25 "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
26 "smc_aper", "swdt", "dbg_trc", "dbg_apb"
27};
28
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080029/**
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +010030 * set_cpu_clk_info() - Setup clock information
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080031 *
32 * This function is called from common code after relocation and sets up the
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +010033 * clock information.
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080034 */
35int set_cpu_clk_info(void)
36{
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +010037 struct clk clk;
38 struct udevice *dev;
39 ulong rate;
40 int i, ret;
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080041
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +010042 ret = uclass_get_device_by_driver(UCLASS_CLK,
43 DM_GET_DRIVER(zynq_clk), &dev);
44 if (ret)
45 return ret;
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080046
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +010047 for (i = 0; i < 2; i++) {
48 clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
49 ret = clk_request(dev, &clk);
50 if (ret < 0)
51 return ret;
52
53 rate = clk_get_rate(&clk) / 1000000;
54 if (i)
55 gd->bd->bi_ddr_freq = rate;
56 else
57 gd->bd->bi_arm_freq = rate;
58
59 clk_free(&clk);
60 }
Michal Simek96a5d4d2014-01-20 11:05:37 +010061 gd->bd->bi_dsp_freq = 0;
62
Soren Brinkmann6c3e61d2013-11-21 13:38:54 -080063 return 0;
64}
65
66/**
Soren Brinkmannd6c9bba2013-11-21 13:39:03 -080067 * soc_clk_dump() - Print clock frequencies
68 * Returns zero on success
69 *
70 * Implementation for the clk dump command.
71 */
72int soc_clk_dump(void)
73{
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +010074 struct udevice *dev;
75 int i, ret;
76
77 ret = uclass_get_device_by_driver(UCLASS_CLK,
78 DM_GET_DRIVER(zynq_clk), &dev);
79 if (ret)
80 return ret;
Soren Brinkmannd6c9bba2013-11-21 13:39:03 -080081
82 printf("clk\t\tfrequency\n");
83 for (i = 0; i < clk_max; i++) {
Stefan Herbrechtsmeierf96fccb2017-01-17 16:27:28 +010084 const char *name = clk_names[i];
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +010085 if (name) {
86 struct clk clk;
87 unsigned long rate;
88
89 clk.id = i;
90 ret = clk_request(dev, &clk);
91 if (ret < 0)
92 return ret;
93
94 rate = clk_get_rate(&clk);
95
96 clk_free(&clk);
97
Michal Simek7ad6d9a2018-02-23 13:39:37 +010098 if ((rate == (unsigned long)-ENOSYS) ||
99 (rate == (unsigned long)-ENXIO))
Stefan Herbrechtsmeier781745b2017-01-17 16:27:30 +0100100 printf("%10s%20s\n", name, "unknown");
101 else
102 printf("%10s%20lu\n", name, rate);
103 }
Soren Brinkmannd6c9bba2013-11-21 13:39:03 -0800104 }
105
106 return 0;
107}