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wdenk384cc682005-04-03 22:35:21 +00001/*
2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_CPU87 1 /* ...on a CPU87 board */
38#define CONFIG_PCI
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050039#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk384cc682005-04-03 22:35:21 +000040
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#ifdef CONFIG_BOOT_ROM
42#define CONFIG_SYS_TEXT_BASE 0xFF800000
43#else
44#define CONFIG_SYS_TEXT_BASE 0xFF000000
45#endif
46
wdenk384cc682005-04-03 22:35:21 +000047/*
48 * select serial console configuration
49 *
50 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
51 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
52 * for SCC).
53 *
54 * if CONFIG_CONS_NONE is defined, then the serial console routines must
55 * defined elsewhere (for example, on the cogent platform, there are serial
56 * ports on the motherboard which are used for the serial console - see
57 * cogent/cma101/serial.[ch]).
58 */
59#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
60#define CONFIG_CONS_ON_SCC /* define if console on SCC */
61#undef CONFIG_CONS_NONE /* define if console on something else*/
62#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
63
64#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
65#define CONFIG_BAUDRATE 230400
66#else
67#define CONFIG_BAUDRATE 9600
68#endif
69
70/*
71 * select ethernet configuration
72 *
73 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
74 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
75 * for FCC)
76 *
77 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050078 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk384cc682005-04-03 22:35:21 +000079 */
80#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
81#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
82#undef CONFIG_ETHER_NONE /* define if ether on something else */
83#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
84
85#define CONFIG_HAS_ETH1 1
86#define CONFIG_HAS_ETH2 1
87
88#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
89
90/*
91 * - Rx-CLK is CLK11
92 * - Tx-CLK is CLK12
93 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
94 * - Enable Full Duplex in FSMR
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
97# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
98# define CONFIG_SYS_CPMFCR_RAMTYPE 0
99# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk384cc682005-04-03 22:35:21 +0000100
101#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
102
103/*
104 * - Rx-CLK is CLK13
105 * - Tx-CLK is CLK14
106 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
107 * - Enable Full Duplex in FSMR
108 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
110# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
111# define CONFIG_SYS_CPMFCR_RAMTYPE 0
112# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk384cc682005-04-03 22:35:21 +0000113
114#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
115
116/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
117#define CONFIG_8260_CLKIN 100000000 /* in Hz */
118
119#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
120
wdenk384cc682005-04-03 22:35:21 +0000121#define CONFIG_PREBOOT \
122 "echo; " \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100123 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
wdenk384cc682005-04-03 22:35:21 +0000124 "echo"
125
126#undef CONFIG_BOOTARGS
127#define CONFIG_BOOTCOMMAND \
128 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100129 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
130 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk384cc682005-04-03 22:35:21 +0000131 "bootm"
132
133/*-----------------------------------------------------------------------
134 * I2C/EEPROM/RTC configuration
135 */
136#define CONFIG_SOFT_I2C /* Software I2C support enabled */
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138# define CONFIG_SYS_I2C_SPEED 50000
139# define CONFIG_SYS_I2C_SLAVE 0xFE
wdenk384cc682005-04-03 22:35:21 +0000140/*
141 * Software (bit-bang) I2C driver configuration
142 */
143#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
144#define I2C_ACTIVE (iop->pdir |= 0x00010000)
145#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
146#define I2C_READ ((iop->pdat & 0x00010000) != 0)
147#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
148 else iop->pdat &= ~0x00010000
149#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
150 else iop->pdat &= ~0x00020000
151#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
152
153#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenk384cc682005-04-03 22:35:21 +0000155
156#undef CONFIG_WATCHDOG /* watchdog disabled */
157
158/*-----------------------------------------------------------------------
159 * Disk-On-Chip configuration
160 */
161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
wdenk384cc682005-04-03 22:35:21 +0000163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_DOC_SUPPORT_2000
165#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
wdenk384cc682005-04-03 22:35:21 +0000166
167/*-----------------------------------------------------------------------
168 * Miscellaneous configuration options
169 */
170
171#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk384cc682005-04-03 22:35:21 +0000173
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500174/*
175 * BOOTP options
176 */
177#define CONFIG_BOOTP_SUBNETMASK
178#define CONFIG_BOOTP_GATEWAY
179#define CONFIG_BOOTP_HOSTNAME
180#define CONFIG_BOOTP_BOOTPATH
181#define CONFIG_BOOTP_BOOTFILESIZE
wdenk384cc682005-04-03 22:35:21 +0000182
wdenk384cc682005-04-03 22:35:21 +0000183
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500184/*
185 * Command line configuration.
186 */
187#include <config_cmd_default.h>
188
189#define CONFIG_CMD_BEDBUG
190#define CONFIG_CMD_DATE
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500191#define CONFIG_CMD_EEPROM
192#define CONFIG_CMD_I2C
193
194#ifdef CONFIG_PCI
195 #define CONFIG_CMD_PCI
196#endif
197
wdenk384cc682005-04-03 22:35:21 +0000198/*
199 * Miscellaneous configurable options
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_LONGHELP /* undef to save memory */
202#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500203#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk384cc682005-04-03 22:35:21 +0000205#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk384cc682005-04-03 22:35:21 +0000207#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
209#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
210#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk384cc682005-04-03 22:35:21 +0000211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
213#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk384cc682005-04-03 22:35:21 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk384cc682005-04-03 22:35:21 +0000216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk384cc682005-04-03 22:35:21 +0000218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk384cc682005-04-03 22:35:21 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
wdenk384cc682005-04-03 22:35:21 +0000222
223#define CONFIG_LOOPW
224
225/*
226 * For booting Linux, the board info and command line data
227 * have to be in the first 8 MB of memory, since this is
228 * the maximum mapped by the Linux kernel during initialization.
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk384cc682005-04-03 22:35:21 +0000231
232/*-----------------------------------------------------------------------
233 * Flash configuration
234 */
235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_BOOTROM_BASE 0xFF800000
237#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
238#define CONFIG_SYS_FLASH_BASE 0xFF000000
239#define CONFIG_SYS_FLASH_SIZE 0x00800000
wdenk384cc682005-04-03 22:35:21 +0000240
241/*-----------------------------------------------------------------------
242 * FLASH organization
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
245#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
wdenk384cc682005-04-03 22:35:21 +0000246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
248#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk384cc682005-04-03 22:35:21 +0000249
250/*-----------------------------------------------------------------------
251 * Other areas to be mapped
252 */
253
254/* CS3: Dual ported SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_DPSRAM_BASE 0x40000000
256#define CONFIG_SYS_DPSRAM_SIZE 0x00100000
wdenk384cc682005-04-03 22:35:21 +0000257
258/* CS4: DiskOnChip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_DOC_BASE 0xF4000000
260#define CONFIG_SYS_DOC_SIZE 0x00100000
wdenk384cc682005-04-03 22:35:21 +0000261
262/* CS5: FDC37C78 controller */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_FDC37C78_BASE 0xF1000000
264#define CONFIG_SYS_FDC37C78_SIZE 0x00100000
wdenk384cc682005-04-03 22:35:21 +0000265
266/* CS6: Board configuration registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_BCRS_BASE 0xF2000000
268#define CONFIG_SYS_BCRS_SIZE 0x00010000
wdenk384cc682005-04-03 22:35:21 +0000269
270/* CS7: VME Extended Access Range */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_VMEEAR_BASE 0x60000000
272#define CONFIG_SYS_VMEEAR_SIZE 0x01000000
wdenk384cc682005-04-03 22:35:21 +0000273
274/* CS8: VME Standard Access Range */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_VMESAR_BASE 0xFE000000
276#define CONFIG_SYS_VMESAR_SIZE 0x01000000
wdenk384cc682005-04-03 22:35:21 +0000277
278/* CS9: VME Short I/O Access Range */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_VMESIOAR_BASE 0xFD000000
280#define CONFIG_SYS_VMESIOAR_SIZE 0x01000000
wdenk384cc682005-04-03 22:35:21 +0000281
282/*-----------------------------------------------------------------------
283 * Hard Reset Configuration Words
284 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk384cc682005-04-03 22:35:21 +0000286 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk384cc682005-04-03 22:35:21 +0000288 */
289#if defined(CONFIG_BOOT_ROM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
wdenk384cc682005-04-03 22:35:21 +0000291 HRCW_BPS01 | HRCW_CS10PC01)
292#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
wdenk384cc682005-04-03 22:35:21 +0000294#endif
295
296/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_HRCW_SLAVE1 0
298#define CONFIG_SYS_HRCW_SLAVE2 0
299#define CONFIG_SYS_HRCW_SLAVE3 0
300#define CONFIG_SYS_HRCW_SLAVE4 0
301#define CONFIG_SYS_HRCW_SLAVE5 0
302#define CONFIG_SYS_HRCW_SLAVE6 0
303#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk384cc682005-04-03 22:35:21 +0000304
305/*-----------------------------------------------------------------------
306 * Internal Memory Mapped Register
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_IMMR 0xF0000000
wdenk384cc682005-04-03 22:35:21 +0000309
310/*-----------------------------------------------------------------------
311 * Definitions for initial stack pointer and data area (in DPRAM)
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200314#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200315#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk384cc682005-04-03 22:35:21 +0000317
318/*-----------------------------------------------------------------------
319 * Start addresses for the final memory configuration
320 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk384cc682005-04-03 22:35:21 +0000322 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
wdenk384cc682005-04-03 22:35:21 +0000324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_SDRAM_BASE 0x00000000
326#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200327#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
329#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenk384cc682005-04-03 22:35:21 +0000330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
332# define CONFIG_SYS_RAMBOOT
wdenk384cc682005-04-03 22:35:21 +0000333#endif
334
335#ifdef CONFIG_PCI
336#define CONFIG_PCI_PNP
337#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk384cc682005-04-03 22:35:21 +0000339#endif
340
341#if 0
342/* environment is in Flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200343#define CONFIG_ENV_IS_IN_FLASH 1
wdenk384cc682005-04-03 22:35:21 +0000344#ifdef CONFIG_BOOT_ROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200346# define CONFIG_ENV_SIZE 0x10000
347# define CONFIG_ENV_SECT_SIZE 0x10000
wdenk384cc682005-04-03 22:35:21 +0000348#endif
349#else
350/* environment is in EEPROM */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200351#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
353#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
wdenk384cc682005-04-03 22:35:21 +0000354/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
356#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
357#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200358#define CONFIG_ENV_OFFSET 512
359#define CONFIG_ENV_SIZE (2048 - 512)
wdenk384cc682005-04-03 22:35:21 +0000360#endif
361
wdenk384cc682005-04-03 22:35:21 +0000362/*-----------------------------------------------------------------------
363 * Cache Configuration
364 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500366#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk384cc682005-04-03 22:35:21 +0000368#endif
369
370/*-----------------------------------------------------------------------
371 * HIDx - Hardware Implementation-dependent Registers 2-11
372 *-----------------------------------------------------------------------
373 * HID0 also contains cache control - initially enable both caches and
374 * invalidate contents, then the final state leaves only the instruction
375 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
376 * but Soft reset does not.
377 *
378 * HID1 has only read-only information - nothing to set.
379 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
wdenk384cc682005-04-03 22:35:21 +0000381 HID0_DCI|HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
383#define CONFIG_SYS_HID2 0
wdenk384cc682005-04-03 22:35:21 +0000384
385/*-----------------------------------------------------------------------
386 * RMR - Reset Mode Register 5-5
387 *-----------------------------------------------------------------------
388 * turn on Checkstop Reset Enable
389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_RMR RMR_CSRE
wdenk384cc682005-04-03 22:35:21 +0000391
392/*-----------------------------------------------------------------------
393 * BCR - Bus Configuration 4-25
394 *-----------------------------------------------------------------------
395 */
396#define BCR_APD01 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
wdenk384cc682005-04-03 22:35:21 +0000398
399/*-----------------------------------------------------------------------
400 * SIUMCR - SIU Module Configuration 4-31
401 *-----------------------------------------------------------------------
402 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
wdenk384cc682005-04-03 22:35:21 +0000404 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
405
406/*-----------------------------------------------------------------------
407 * SYPCR - System Protection Control 4-35
408 * SYPCR can only be written once after reset!
409 *-----------------------------------------------------------------------
410 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
411 */
412#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk384cc682005-04-03 22:35:21 +0000414 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
415#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk384cc682005-04-03 22:35:21 +0000417 SYPCR_SWRI|SYPCR_SWP)
418#endif /* CONFIG_WATCHDOG */
419
420/*-----------------------------------------------------------------------
421 * TMCNTSC - Time Counter Status and Control 4-40
422 *-----------------------------------------------------------------------
423 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
424 * and enable Time Counter
425 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk384cc682005-04-03 22:35:21 +0000427
428/*-----------------------------------------------------------------------
429 * PISCR - Periodic Interrupt Status and Control 4-42
430 *-----------------------------------------------------------------------
431 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
432 * Periodic timer
433 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk384cc682005-04-03 22:35:21 +0000435
436/*-----------------------------------------------------------------------
437 * SCCR - System Clock Control 9-8
438 *-----------------------------------------------------------------------
439 * Ensure DFBRG is Divide by 16
440 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_SCCR SCCR_DFBRG01
wdenk384cc682005-04-03 22:35:21 +0000442
443/*-----------------------------------------------------------------------
444 * RCCR - RISC Controller Configuration 13-7
445 *-----------------------------------------------------------------------
446 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_RCCR 0
wdenk384cc682005-04-03 22:35:21 +0000448
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
wdenk384cc682005-04-03 22:35:21 +0000450
451/*
Wolfgang Denkfd279962006-07-22 21:45:49 +0200452 * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
wdenk384cc682005-04-03 22:35:21 +0000453 * refresh rate = 7.68 uS (100 MHz Bus Clock)
454 */
455
456/*-----------------------------------------------------------------------
457 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
458 *-----------------------------------------------------------------------
459 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_MPTPR 0x2000
wdenk384cc682005-04-03 22:35:21 +0000461
462/*-----------------------------------------------------------------------
463 * PSRT - Refresh Timer Register 10-16
464 *-----------------------------------------------------------------------
465 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_PSRT 0x16
wdenk384cc682005-04-03 22:35:21 +0000467
468/*-----------------------------------------------------------------------
469 * PSRT - SDRAM Mode Register 10-10
470 *-----------------------------------------------------------------------
471 */
472
473 /* SDRAM initialization values for 8-column chips
474 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
wdenk384cc682005-04-03 22:35:21 +0000476 ORxS_BPD_4 |\
477 ORxS_ROWST_PBI0_A9 |\
478 ORxS_NUMR_12)
479
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
wdenk384cc682005-04-03 22:35:21 +0000481 PSDMR_BSMA_A14_A16 |\
482 PSDMR_SDA10_PBI0_A10 |\
483 PSDMR_RFRC_7_CLK |\
484 PSDMR_PRETOACT_2W |\
485 PSDMR_ACTTORW_2W |\
486 PSDMR_LDOTOPRE_1C |\
487 PSDMR_WRC_1C |\
488 PSDMR_CL_2)
489
490 /* SDRAM initialization values for 9-column chips
491 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
wdenk384cc682005-04-03 22:35:21 +0000493 ORxS_BPD_4 |\
494 ORxS_ROWST_PBI0_A7 |\
495 ORxS_NUMR_13)
496
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
wdenk384cc682005-04-03 22:35:21 +0000498 PSDMR_BSMA_A13_A15 |\
499 PSDMR_SDA10_PBI0_A9 |\
500 PSDMR_RFRC_7_CLK |\
501 PSDMR_PRETOACT_2W |\
502 PSDMR_ACTTORW_2W |\
503 PSDMR_LDOTOPRE_1C |\
504 PSDMR_WRC_1C |\
505 PSDMR_CL_2)
506
Wolfgang Denkfd279962006-07-22 21:45:49 +0200507 /* SDRAM initialization values for 10-column chips
508 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_OR2_10COL (CONFIG_SYS_MIN_AM_MASK |\
Wolfgang Denkfd279962006-07-22 21:45:49 +0200510 ORxS_BPD_4 |\
511 ORxS_ROWST_PBI1_A4 |\
512 ORxS_NUMR_13)
513
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\
Wolfgang Denkfd279962006-07-22 21:45:49 +0200515 PSDMR_SDAM_A17_IS_A5 |\
516 PSDMR_BSMA_A13_A15 |\
517 PSDMR_SDA10_PBI1_A6 |\
518 PSDMR_RFRC_7_CLK |\
519 PSDMR_PRETOACT_2W |\
520 PSDMR_ACTTORW_2W |\
521 PSDMR_LDOTOPRE_1C |\
522 PSDMR_WRC_1C |\
523 PSDMR_CL_2)
Wolfgang Denk16850912006-08-27 18:10:01 +0200524
wdenk384cc682005-04-03 22:35:21 +0000525/*
526 * Init Memory Controller:
527 *
528 * Bank Bus Machine PortSz Device
529 * ---- --- ------- ------ ------
530 * 0 60x GPCM 8 bit Boot ROM
531 * 1 60x GPCM 64 bit FLASH
532 * 2 60x SDRAM 64 bit SDRAM
533 *
534 */
535
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536#define CONFIG_SYS_MRS_OFFS 0x00000000
wdenk384cc682005-04-03 22:35:21 +0000537
538#ifdef CONFIG_BOOT_ROM
539/* Bank 0 - Boot ROM
540 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
wdenk384cc682005-04-03 22:35:21 +0000542 BRx_PS_8 |\
543 BRx_MS_GPCM_P |\
544 BRx_V)
545
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000547 ORxG_CSNT |\
548 ORxG_ACS_DIV1 |\
549 ORxG_SCY_5_CLK |\
550 ORxU_EHTR_8IDLE)
551
552/* Bank 1 - FLASH
553 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200554#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000555 BRx_PS_64 |\
556 BRx_MS_GPCM_P |\
557 BRx_V)
558
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200559#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000560 ORxG_CSNT |\
561 ORxG_ACS_DIV1 |\
562 ORxG_SCY_5_CLK |\
563 ORxU_EHTR_8IDLE)
564
565#else /* CONFIG_BOOT_ROM */
566/* Bank 0 - FLASH
567 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200568#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000569 BRx_PS_64 |\
570 BRx_MS_GPCM_P |\
571 BRx_V)
572
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000574 ORxG_CSNT |\
575 ORxG_ACS_DIV1 |\
576 ORxG_SCY_5_CLK |\
577 ORxU_EHTR_8IDLE)
578
579/* Bank 1 - Boot ROM
580 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
wdenk384cc682005-04-03 22:35:21 +0000582 BRx_PS_8 |\
583 BRx_MS_GPCM_P |\
584 BRx_V)
585
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200586#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000587 ORxG_CSNT |\
588 ORxG_ACS_DIV1 |\
589 ORxG_SCY_5_CLK |\
590 ORxU_EHTR_8IDLE)
591
592#endif /* CONFIG_BOOT_ROM */
593
594
595/* Bank 2 - 60x bus SDRAM
596 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597#ifndef CONFIG_SYS_RAMBOOT
598#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000599 BRx_PS_64 |\
600 BRx_MS_SDRAM_P |\
601 BRx_V)
602
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200603#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
wdenk384cc682005-04-03 22:35:21 +0000604
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200605#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
606#endif /* CONFIG_SYS_RAMBOOT */
wdenk384cc682005-04-03 22:35:21 +0000607
608/* Bank 3 - Dual Ported SRAM
609 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200610#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000611 BRx_PS_16 |\
612 BRx_MS_GPCM_P |\
613 BRx_V)
614
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200615#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000616 ORxG_CSNT |\
617 ORxG_ACS_DIV1 |\
618 ORxG_SCY_7_CLK |\
619 ORxG_SETA)
620
621/* Bank 4 - DiskOnChip
622 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200623#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000624 BRx_PS_8 |\
625 BRx_MS_GPCM_P |\
626 BRx_V)
627
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200628#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000629 ORxG_CSNT |\
630 ORxG_ACS_DIV2 |\
631 ORxG_SCY_9_CLK |\
632 ORxU_EHTR_8IDLE)
633
634/* Bank 5 - FDC37C78 controller
635 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200636#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000637 BRx_PS_8 |\
638 BRx_MS_GPCM_P |\
639 BRx_V)
640
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200641#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000642 ORxG_ACS_DIV2 |\
643 ORxG_SCY_10_CLK |\
644 ORxU_EHTR_8IDLE)
645
646/* Bank 6 - Board control registers
647 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200648#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000649 BRx_PS_8 |\
650 BRx_MS_GPCM_P |\
651 BRx_V)
652
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200653#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000654 ORxG_CSNT |\
655 ORxG_SCY_7_CLK)
656
657/* Bank 7 - VME Extended Access Range
658 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200659#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000660 BRx_PS_32 |\
661 BRx_MS_GPCM_P |\
662 BRx_V)
663
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200664#define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000665 ORxG_CSNT |\
666 ORxG_ACS_DIV1 |\
667 ORxG_SCY_7_CLK |\
668 ORxG_SETA)
669
670/* Bank 8 - VME Standard Access Range
671 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200672#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000673 BRx_PS_16 |\
674 BRx_MS_GPCM_P |\
675 BRx_V)
676
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200677#define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000678 ORxG_CSNT |\
679 ORxG_ACS_DIV1 |\
680 ORxG_SCY_7_CLK |\
681 ORxG_SETA)
682
683/* Bank 9 - VME Short I/O Access Range
684 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200685#define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
wdenk384cc682005-04-03 22:35:21 +0000686 BRx_PS_16 |\
687 BRx_MS_GPCM_P |\
688 BRx_V)
689
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200690#define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\
wdenk384cc682005-04-03 22:35:21 +0000691 ORxG_CSNT |\
692 ORxG_ACS_DIV1 |\
693 ORxG_SCY_7_CLK |\
694 ORxG_SETA)
695
696#endif /* __CONFIG_H */