| wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2004 Sascha Hauer, Pengutronix |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version 2 |
| 7 | * of the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA |
| 17 | * 02111-1307, USA. |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #include <config.h> |
| 22 | #include <version.h> |
| 23 | #include <asm/arch/imx-regs.h> |
| 24 | |
| 25 | .globl memsetup |
| 26 | memsetup: |
| 27 | |
| 28 | mov r10, lr |
| 29 | |
| 30 | /* Change PERCLK1DIV to 14 ie 14+1 */ |
| 31 | ldr r0, =PCDR |
| 32 | ldr r1, =CFG_PCDR_VAL |
| 33 | str r1, [r0] |
| 34 | |
| 35 | /* set MCU PLL Control Register 0 */ |
| 36 | |
| 37 | ldr r0, =MPCTL0 |
| 38 | ldr r1, =CFG_MPCTL0_VAL |
| 39 | str r1, [r0] |
| 40 | |
| 41 | /* set MCU PLL Control Register 1 */ |
| 42 | |
| 43 | ldr r0, =MPCTL1 |
| 44 | ldr r1, =CFG_MPCTL1_VAL |
| 45 | str r1, [r0] |
| 46 | |
| 47 | /* set mpll restart bit */ |
| 48 | ldr r0, =CSCR |
| 49 | ldr r1, [r0] |
| 50 | orr r1,r1,#(1<<21) |
| 51 | str r1, [r0] |
| 52 | |
| 53 | mov r2,#0x10 |
| 54 | 1: |
| 55 | mov r3,#0x2000 |
| 56 | 2: |
| 57 | subs r3,r3,#1 |
| 58 | bne 2b |
| 59 | |
| 60 | subs r2,r2,#1 |
| 61 | bne 1b |
| 62 | |
| 63 | /* set System PLL Control Register 0 */ |
| 64 | |
| 65 | ldr r0, =SPCTL0 |
| 66 | ldr r1, =CFG_SPCTL0_VAL |
| 67 | str r1, [r0] |
| 68 | |
| 69 | /* set System PLL Control Register 1 */ |
| 70 | |
| 71 | ldr r0, =SPCTL1 |
| 72 | ldr r1, =CFG_SPCTL1_VAL |
| 73 | str r1, [r0] |
| 74 | |
| 75 | /* set spll restart bit */ |
| 76 | ldr r0, =CSCR |
| 77 | ldr r1, [r0] |
| 78 | orr r1,r1,#(1<<22) |
| 79 | str r1, [r0] |
| 80 | |
| 81 | mov r2,#0x10 |
| 82 | 1: |
| 83 | mov r3,#0x2000 |
| 84 | 2: |
| 85 | subs r3,r3,#1 |
| 86 | bne 2b |
| 87 | |
| 88 | subs r2,r2,#1 |
| 89 | bne 1b |
| 90 | |
| 91 | ldr r0, =CSCR |
| 92 | ldr r1, =CFG_CSCR_VAL |
| 93 | str r1, [r0] |
| 94 | |
| 95 | ldr r0, =GPCR |
| 96 | ldr r1, =CFG_GPCR_VAL |
| 97 | str r1, [r0] |
| 98 | |
| 99 | /* |
| 100 | * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon |
| 101 | * this..... |
| 102 | * |
| 103 | * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 |
| 104 | * register 1, this stops it using the output of the PLL and thus runs at the |
| 105 | * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never |
| 106 | * use the value set in the CM_OSC registers...regardless of what you set it |
| 107 | * too! Thus, although i thought i was running at 140MHz, i'm actually running |
| 108 | * at 40!.. |
| 109 | * |
| 110 | * Slapping this into my bootloader does the trick... |
| 111 | * |
| 112 | * MRC p15,0,r0,c1,c0,0 ; read core configuration register |
| 113 | * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode |
| 114 | * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration |
| 115 | * register |
| 116 | * |
| 117 | */ |
| 118 | MRC p15,0,r0,c1,c0,0 |
| 119 | /* ORR r0,r0,#0xC0000000 async mode */ |
| 120 | /* ORR r0,r0,#0x40000000 sync mode */ |
| 121 | ORR r0,r0,#0xC0000000 |
| 122 | MCR p15,0,r0,c1,c0,0 |
| 123 | |
| 124 | ldr r0, =GIUS(0) |
| 125 | ldr r1, =CFG_GIUS_A_VAL |
| 126 | str r1, [r0] |
| 127 | |
| 128 | ldr r0, =FMCR |
| 129 | ldr r1, =CFG_FMCR_VAL |
| 130 | str r1, [r0] |
| 131 | |
| 132 | ldr r0, =CS0U |
| 133 | ldr r1, =CFG_CS0U_VAL |
| 134 | str r1, [r0] |
| 135 | |
| 136 | ldr r0, =CS0L |
| 137 | ldr r1, =CFG_CS0L_VAL |
| 138 | str r1, [r0] |
| 139 | |
| 140 | ldr r0, =CS1U |
| 141 | ldr r1, =CFG_CS1U_VAL |
| 142 | str r1, [r0] |
| 143 | |
| 144 | ldr r0, =CS1L |
| 145 | ldr r1, =CFG_CS1L_VAL |
| 146 | str r1, [r0] |
| 147 | |
| 148 | ldr r0, =CS4U |
| 149 | ldr r1, =CFG_CS4U_VAL |
| 150 | str r1, [r0] |
| 151 | |
| 152 | ldr r0, =CS4L |
| 153 | ldr r1, =CFG_CS4L_VAL |
| 154 | str r1, [r0] |
| 155 | |
| 156 | ldr r0, =CS5U |
| 157 | ldr r1, =CFG_CS5U_VAL |
| 158 | str r1, [r0] |
| 159 | |
| 160 | ldr r0, =CS5L |
| 161 | ldr r1, =CFG_CS5L_VAL |
| 162 | str r1, [r0] |
| 163 | |
| 164 | /* SDRAM Setup */ |
| 165 | |
| 166 | ldr r1,=0x00221000 /* adr of SDCTRL0 */ |
| 167 | ldr r0,=0x92120200 |
| 168 | str r0,[r1,#0] /* put in precharge command mode */ |
| 169 | ldr r2,=0x08200000 /* adr for precharge cmd */ |
| 170 | ldr r0,[r2,#0] /* precharge */ |
| 171 | ldr r0,=0xA2120200 |
| 172 | ldr r2,=0x08000000 /* start of SDRAM */ |
| 173 | str r0,[r1,#0] /* put in auto-refresh mode */ |
| 174 | ldr r0,[r2,#0] /* auto-refresh */ |
| 175 | ldr r0,[r2,#0] /* auto-refresh */ |
| 176 | ldr r0,[r2,#0] /* auto-refresh */ |
| 177 | ldr r0,[r2,#0] /* auto-refresh */ |
| 178 | ldr r0,[r2,#0] /* auto-refresh */ |
| 179 | ldr r0,[r2,#0] /* auto-refresh */ |
| 180 | ldr r0,[r2,#0] /* auto-refresh */ |
| 181 | ldr r0,=0xB2120200 |
| 182 | ldr r2,=0x08111800 |
| 183 | str r0,[r1,#0] /* setup for mode register of SDRAM */ |
| 184 | ldr r0,[r2,#0] /* program mode register */ |
| 185 | ldr r0,=0x82124267 |
| 186 | str r0,[r1,#0] /* back to normal operation */ |
| 187 | |
| 188 | mov pc,r10 |