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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
wdenk8bde7f72003-06-27 21:31:46 +000025#include <command.h>
wdenkc6097192002-11-03 00:24:07 +000026#include "w7o.h"
27#include <asm/processor.h>
28
29#include "vpd.h"
30#include "errors.h"
31#include <watchdog.h>
32
wdenkc83bf6a2004-01-06 22:38:14 +000033unsigned long get_dram_size (void);
Stefan Roesebbeff302008-06-02 17:37:28 +020034void sdram_init(void);
wdenkc6097192002-11-03 00:24:07 +000035
36/*
37 * Macros to transform values
38 * into environment strings.
39 */
40#define XMK_STR(x) #x
41#define MK_STR(x) XMK_STR(x)
42
43/* ------------------------------------------------------------------------- */
44
wdenkc837dcb2004-01-20 23:12:12 +000045int board_early_init_f (void)
wdenkc6097192002-11-03 00:24:07 +000046{
47#if defined(CONFIG_W7OLMG)
wdenkc83bf6a2004-01-06 22:38:14 +000048 /*
49 * Setup GPIO pins - reset devices.
50 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020051 out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
52 out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
53 out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
wdenkc6097192002-11-03 00:24:07 +000054
wdenkc83bf6a2004-01-06 22:38:14 +000055 /*
56 * IRQ 0-15 405GP internally generated; active high; level sensitive
57 * IRQ 16 405GP internally generated; active low; level sensitive
58 * IRQ 17-24 RESERVED
59 * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
60 * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
61 * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
62 * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
63 * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
64 * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
65 * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
66 */
Stefan Roese952e7762009-09-24 09:55:50 +020067 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
68 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
wdenkc6097192002-11-03 00:24:07 +000069
Stefan Roese952e7762009-09-24 09:55:50 +020070 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
71 mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
72 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
73 mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
wdenkc83bf6a2004-01-06 22:38:14 +000074 INT0 highest priority */
wdenkc6097192002-11-03 00:24:07 +000075
Stefan Roese952e7762009-09-24 09:55:50 +020076 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
wdenkc6097192002-11-03 00:24:07 +000077
78#elif defined(CONFIG_W7OLMC)
wdenkc83bf6a2004-01-06 22:38:14 +000079 /*
80 * Setup GPIO pins
81 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020082 out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
83 out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
84 out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
wdenkc6097192002-11-03 00:24:07 +000085
wdenkc83bf6a2004-01-06 22:38:14 +000086 /*
87 * IRQ 0-15 405GP internally generated; active high; level sensitive
88 * IRQ 16 405GP internally generated; active low; level sensitive
89 * IRQ 17-24 RESERVED
90 * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
91 * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
92 * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
93 * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
94 * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
95 * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
96 * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
97 */
Stefan Roese952e7762009-09-24 09:55:50 +020098 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
99 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
wdenkc6097192002-11-03 00:24:07 +0000100
Stefan Roese952e7762009-09-24 09:55:50 +0200101 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
102 mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
103 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
104 mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
wdenkc83bf6a2004-01-06 22:38:14 +0000105 INT0 highest priority */
wdenkc6097192002-11-03 00:24:07 +0000106
Stefan Roese952e7762009-09-24 09:55:50 +0200107 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
wdenkc6097192002-11-03 00:24:07 +0000108
wdenkc83bf6a2004-01-06 22:38:14 +0000109#else /* Unknown */
wdenkc6097192002-11-03 00:24:07 +0000110# error "Unknown W7O board configuration"
111#endif
112
wdenkc83bf6a2004-01-06 22:38:14 +0000113 WATCHDOG_RESET (); /* Reset the watchdog */
114 temp_uart_init (); /* init the uart for debug */
115 WATCHDOG_RESET (); /* Reset the watchdog */
116 test_led (); /* test the LEDs */
117 test_sdram (get_dram_size ()); /* test the dram */
118 log_stat (ERR_POST1); /* log status,post1 complete */
119 return 0;
wdenkc6097192002-11-03 00:24:07 +0000120}
121
122
123/* ------------------------------------------------------------------------- */
124
125/*
126 * Check Board Identity:
127 */
128int checkboard (void)
129{
wdenkc83bf6a2004-01-06 22:38:14 +0000130 VPD vpd;
wdenkc6097192002-11-03 00:24:07 +0000131
wdenkc83bf6a2004-01-06 22:38:14 +0000132 puts ("Board: ");
wdenkc6097192002-11-03 00:24:07 +0000133
wdenkc83bf6a2004-01-06 22:38:14 +0000134 /* VPD data present in I2C EEPROM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135 if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
wdenkc83bf6a2004-01-06 22:38:14 +0000136 /*
137 * Known board type.
138 */
139 if (vpd.productId[0] &&
140 ((strncmp (vpd.productId, "GMM", 3) == 0) ||
141 (strncmp (vpd.productId, "CMM", 3) == 0))) {
wdenkc6097192002-11-03 00:24:07 +0000142
wdenkc83bf6a2004-01-06 22:38:14 +0000143 /* Output board information on startup */
144 printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
145 return (0);
146 }
wdenkc6097192002-11-03 00:24:07 +0000147 }
wdenkc6097192002-11-03 00:24:07 +0000148
wdenkc83bf6a2004-01-06 22:38:14 +0000149 puts ("### Unknown HW ID - assuming NOTHING\n");
150 return (0);
wdenkc6097192002-11-03 00:24:07 +0000151}
152
153/* ------------------------------------------------------------------------- */
154
Becky Bruce9973e3c2008-06-09 16:03:40 -0500155phys_size_t initdram (int board_type)
wdenkc6097192002-11-03 00:24:07 +0000156{
Stefan Roesebbeff302008-06-02 17:37:28 +0200157 /*
158 * ToDo: Move the asm init routine sdram_init() to this C file,
159 * or even better use some common ppc4xx code available
Stefan Roesea47a12b2010-04-15 16:07:28 +0200160 * in arch/powerpc/cpu/ppc4xx
Stefan Roesebbeff302008-06-02 17:37:28 +0200161 */
162 sdram_init();
163
wdenkc83bf6a2004-01-06 22:38:14 +0000164 return get_dram_size ();
wdenkc6097192002-11-03 00:24:07 +0000165}
166
167unsigned long get_dram_size (void)
168{
wdenkc83bf6a2004-01-06 22:38:14 +0000169 int tmp, i, regs[4];
170 int size = 0;
wdenkc6097192002-11-03 00:24:07 +0000171
wdenkc83bf6a2004-01-06 22:38:14 +0000172 /* Get bank Size registers */
Stefan Roese95b602b2009-09-24 13:59:57 +0200173 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200174 regs[0] = mfdcr (SDRAM0_CFGDATA);
wdenkc6097192002-11-03 00:24:07 +0000175
Stefan Roese95b602b2009-09-24 13:59:57 +0200176 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200177 regs[1] = mfdcr (SDRAM0_CFGDATA);
wdenkc6097192002-11-03 00:24:07 +0000178
Stefan Roese95b602b2009-09-24 13:59:57 +0200179 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200180 regs[2] = mfdcr (SDRAM0_CFGDATA);
wdenkc6097192002-11-03 00:24:07 +0000181
Stefan Roese95b602b2009-09-24 13:59:57 +0200182 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200183 regs[3] = mfdcr (SDRAM0_CFGDATA);
wdenkc6097192002-11-03 00:24:07 +0000184
wdenkc83bf6a2004-01-06 22:38:14 +0000185 /* compute the size, add each bank if enabled */
186 for (i = 0; i < 4; i++) {
187 if (regs[i] & 0x0001) { /* if enabled, */
188 tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
189 tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
190 size += tmp;
191 }
wdenkc6097192002-11-03 00:24:07 +0000192 }
wdenkc6097192002-11-03 00:24:07 +0000193
wdenkc83bf6a2004-01-06 22:38:14 +0000194 return size;
wdenkc6097192002-11-03 00:24:07 +0000195}
196
197int misc_init_f (void)
198{
wdenkc83bf6a2004-01-06 22:38:14 +0000199 return 0;
wdenkc6097192002-11-03 00:24:07 +0000200}
201
wdenkc83bf6a2004-01-06 22:38:14 +0000202static void w7o_env_init (VPD * vpd)
wdenkc6097192002-11-03 00:24:07 +0000203{
wdenkc83bf6a2004-01-06 22:38:14 +0000204 /*
205 * Read VPD
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207 if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
wdenkc83bf6a2004-01-06 22:38:14 +0000208 return;
wdenkc6097192002-11-03 00:24:07 +0000209
wdenkc83bf6a2004-01-06 22:38:14 +0000210 /*
211 * Known board type.
212 */
213 if (vpd->productId[0] &&
214 ((strncmp (vpd->productId, "GMM", 3) == 0) ||
215 (strncmp (vpd->productId, "CMM", 3) == 0))) {
216 char buf[30];
217 char *eth;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200218 char *serial = getenv ("serial#");
219 char *ethaddr = getenv ("ethaddr");
wdenkc6097192002-11-03 00:24:07 +0000220
wdenkc83bf6a2004-01-06 22:38:14 +0000221 /* Set 'serial#' envvar if serial# isn't set */
222 if (!serial) {
223 sprintf (buf, "%s-%ld", vpd->productId,
224 vpd->serialNum);
225 setenv ("serial#", buf);
226 }
227
228 /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200229 eth = (char *)(vpd->ethAddrs[0]);
wdenkc83bf6a2004-01-06 22:38:14 +0000230 if (ethaddr
231 && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
232 /* Now setup ethaddr */
233 sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
234 eth[0], eth[1], eth[2], eth[3], eth[4],
235 eth[5]);
236 setenv ("ethaddr", buf);
237 }
wdenkc6097192002-11-03 00:24:07 +0000238 }
wdenkc83bf6a2004-01-06 22:38:14 +0000239} /* w7o_env_init() */
wdenkc6097192002-11-03 00:24:07 +0000240
241
242int misc_init_r (void)
243{
wdenkc83bf6a2004-01-06 22:38:14 +0000244 VPD vpd; /* VPD information */
wdenkc6097192002-11-03 00:24:07 +0000245
246#if defined(CONFIG_W7OLMG)
wdenkc83bf6a2004-01-06 22:38:14 +0000247 unsigned long greg; /* GPIO Register */
wdenkc6097192002-11-03 00:24:07 +0000248
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200249 greg = in32 (PPC405GP_GPIO0_OR);
wdenkc6097192002-11-03 00:24:07 +0000250
wdenkc83bf6a2004-01-06 22:38:14 +0000251 /*
252 * XXX - Unreset devices - this should be moved into VxWorks driver code
253 */
254 greg |= 0x41800000L; /* SAM, PHY, Galileo */
wdenkc6097192002-11-03 00:24:07 +0000255
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200256 out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
wdenkc6097192002-11-03 00:24:07 +0000257#endif /* CONFIG_W7OLMG */
258
wdenkc83bf6a2004-01-06 22:38:14 +0000259 /*
260 * Initialize W7O environment variables
261 */
262 w7o_env_init (&vpd);
wdenkc6097192002-11-03 00:24:07 +0000263
wdenkc83bf6a2004-01-06 22:38:14 +0000264 /*
265 * Initialize the FPGA(s).
266 */
267 if (init_fpga () == 0)
268 test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
wdenkc6097192002-11-03 00:24:07 +0000269
wdenkc83bf6a2004-01-06 22:38:14 +0000270 /* More POST testing. */
271 post2 ();
wdenkc6097192002-11-03 00:24:07 +0000272
wdenkc83bf6a2004-01-06 22:38:14 +0000273 /* Done with hardware initialization and POST. */
274 log_stat (ERR_POSTOK);
wdenkc6097192002-11-03 00:24:07 +0000275
wdenkc83bf6a2004-01-06 22:38:14 +0000276 /* Call silly, fail safe boot init routine */
277 init_fsboot ();
wdenkc6097192002-11-03 00:24:07 +0000278
279 return (0);
280}