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Sanjeev Premi39708842011-10-25 06:11:30 +00001/*
2 * Common configuration settings for the TI OMAP3 EVM board.
3 *
4 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __OMAP3_EVM_COMMON_H
18#define __OMAP3_EVM_COMMON_H
19
20/*
21 * High level configuration options
22 */
23#define CONFIG_OMAP /* This is TI OMAP core */
24#define CONFIG_OMAP34XX /* belonging to 34XX family */
Sanjeev Premi39708842011-10-25 06:11:30 +000025
26#define CONFIG_SDRC /* The chip has SDRC controller */
27
28#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
Sanjeev Premi39708842011-10-25 06:11:30 +000029#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
30
31#undef CONFIG_USE_IRQ /* no support for IRQs */
32
33/*
34 * Clock related definitions
35 */
36#define V_OSCK 26000000 /* Clock output from T2 */
37#define V_SCLK (V_OSCK >> 1)
38
39/*
40 * OMAP3 has 12 GP timers, they can be driven by the system clock
41 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
42 * This rate is divided by a local divisor.
43 */
44#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
45#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
46#define CONFIG_SYS_HZ 1000
47
48/* Size of environment - 128KB */
49#define CONFIG_ENV_SIZE (128 << 10)
50
51/* Size of malloc pool */
52#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
53
54/*
55 * Stack sizes
56 * These values are used in start.S
57 */
58#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
59
Sanjeev Premi39708842011-10-25 06:11:30 +000060/*
61 * Physical Memory Map
62 * Note 1: CS1 may or may not be populated
63 * Note 2: SDRAM size is expected to be at least 32MB
64 */
65#define CONFIG_NR_DRAM_BANKS 2
66#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Sanjeev Premi39708842011-10-25 06:11:30 +000067#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
68
Sanjeev Premi39708842011-10-25 06:11:30 +000069/* Limits for memtest */
70#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
71#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
72 0x01F00000) /* 31MB */
73
74/* Default load address */
75#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
76
77/* -----------------------------------------------------------------------------
78 * Hardware drivers
79 * -----------------------------------------------------------------------------
80 */
81
82/*
83 * NS16550 Configuration
84 */
85#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
86
87#define CONFIG_SYS_NS16550
88#define CONFIG_SYS_NS16550_SERIAL
89#define CONFIG_SYS_NS16550_REG_SIZE (-4)
90#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
91
92/*
93 * select serial console configuration
94 */
95#define CONFIG_CONS_INDEX 1
96#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
97#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
98#define CONFIG_BAUDRATE 115200
99#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
100 115200}
101
102/*
103 * I2C
104 */
105#define CONFIG_HARD_I2C
106#define CONFIG_DRIVER_OMAP34XX_I2C
107
108#define CONFIG_SYS_I2C_SPEED 100000
109#define CONFIG_SYS_I2C_SLAVE 1
110#define CONFIG_SYS_I2C_BUS 0
111#define CONFIG_SYS_I2C_BUS_SELECT 1
112
113/*
114 * PISMO support
115 */
116#define PISMO1_NAND_SIZE GPMC_SIZE_128M
117#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
118
119/* Monitor at start of flash - Reserve 2 sectors */
120#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
121
122#define CONFIG_SYS_MONITOR_LEN (256 << 10)
123
124/* Start location & size of environment */
125#define ONENAND_ENV_OFFSET 0x260000
126#define SMNAND_ENV_OFFSET 0x260000
127
128#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
129
130/*
131 * NAND
132 */
133/* Physical address to access NAND */
134#define CONFIG_SYS_NAND_ADDR NAND_BASE
135
136/* Physical address to access NAND at CS0 */
137#define CONFIG_SYS_NAND_BASE NAND_BASE
138
139/* Max number of NAND devices */
140#define CONFIG_SYS_MAX_NAND_DEVICE 1
141
142/* Timeout values (in ticks) */
143#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
144#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
145
146/* Flash banks JFFS2 should use */
147#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
148 CONFIG_SYS_MAX_NAND_DEVICE)
149
150#define CONFIG_SYS_JFFS2_MEM_NAND
151#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
152#define CONFIG_SYS_JFFS2_NUM_BANKS 1
153
154#define CONFIG_JFFS2_NAND
155/* nand device jffs2 lives on */
156#define CONFIG_JFFS2_DEV "nand0"
157/* Start of jffs2 partition */
158#define CONFIG_JFFS2_PART_OFFSET 0x680000
159/* Size of jffs2 partition */
160#define CONFIG_JFFS2_PART_SIZE 0xf980000
161
162/*
163 * USB
164 */
165#ifdef CONFIG_USB_OMAP3
166
167#ifdef CONFIG_MUSB_HCD
168#define CONFIG_CMD_USB
169
170#define CONFIG_USB_STORAGE
171#define CONGIG_CMD_STORAGE
172#define CONFIG_CMD_FAT
173
174#ifdef CONFIG_USB_KEYBOARD
175#define CONFIG_SYS_USB_EVENT_POLL
176#define CONFIG_PREBOOT "usb start"
177#endif /* CONFIG_USB_KEYBOARD */
178
179#endif /* CONFIG_MUSB_HCD */
180
181#ifdef CONFIG_MUSB_UDC
182/* USB device configuration */
183#define CONFIG_USB_DEVICE
184#define CONFIG_USB_TTY
185#define CONFIG_SYS_CONSOLE_IS_IN_ENV
186
187/* Change these to suit your needs */
188#define CONFIG_USBD_VENDORID 0x0451
189#define CONFIG_USBD_PRODUCTID 0x5678
190#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
191#define CONFIG_USBD_PRODUCT_NAME "EVM"
192#endif /* CONFIG_MUSB_UDC */
193
194#endif /* CONFIG_USB_OMAP3 */
195
196/* ----------------------------------------------------------------------------
197 * U-boot features
198 * ----------------------------------------------------------------------------
199 */
200#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
201#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
202#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
203
204#define CONFIG_MISC_INIT_R
205
206#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
207#define CONFIG_SETUP_MEMORY_TAGS
208#define CONFIG_INITRD_TAG
209#define CONFIG_REVISION_TAG
210
211/* Size of Console IO buffer */
212#define CONFIG_SYS_CBSIZE 512
213
214/* Size of print buffer */
215#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
216 sizeof(CONFIG_SYS_PROMPT) + 16)
217
218/* Size of bootarg buffer */
219#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
220
221#define CONFIG_BOOTFILE "uImage"
222
223/*
224 * NAND / OneNAND
225 */
226#if defined(CONFIG_CMD_NAND)
227#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
228
229#define CONFIG_NAND_OMAP_GPMC
230#define GPMC_NAND_ECC_LP_x16_LAYOUT
Sanjeev Premi39708842011-10-25 06:11:30 +0000231#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
232#elif defined(CONFIG_CMD_ONENAND)
233#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
234#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
Sanjeev Premiedc633e2011-10-25 06:11:33 +0000235#endif
Sanjeev Premi39708842011-10-25 06:11:30 +0000236
Sanjeev Premiedc633e2011-10-25 06:11:33 +0000237#if !defined(CONFIG_ENV_IS_NOWHERE)
238#if defined(CONFIG_CMD_NAND)
239#define CONFIG_ENV_IS_IN_NAND
240#elif defined(CONFIG_CMD_ONENAND)
Sanjeev Premi39708842011-10-25 06:11:30 +0000241#define CONFIG_ENV_IS_IN_ONENAND
242#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
243#endif
Sanjeev Premiedc633e2011-10-25 06:11:33 +0000244#endif /* CONFIG_ENV_IS_NOWHERE */
Sanjeev Premi39708842011-10-25 06:11:30 +0000245
246#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
247
248#if defined(CONFIG_CMD_NET)
249
250/* Ethernet (SMSC9115 from SMSC9118 family) */
Sanjeev Premi39708842011-10-25 06:11:30 +0000251#define CONFIG_SMC911X
252#define CONFIG_SMC911X_32_BIT
253#define CONFIG_SMC911X_BASE 0x2C000000
254
255/* BOOTP fields */
256#define CONFIG_BOOTP_SUBNETMASK 0x00000001
257#define CONFIG_BOOTP_GATEWAY 0x00000002
258#define CONFIG_BOOTP_HOSTNAME 0x00000004
259#define CONFIG_BOOTP_BOOTPATH 0x00000010
260
261#endif /* CONFIG_CMD_NET */
262
263/* Support for relocation */
264#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
265#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
266#define CONFIG_SYS_INIT_RAM_SIZE 0x800
267#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
268 CONFIG_SYS_INIT_RAM_SIZE - \
269 GENERATED_GBL_DATA_SIZE)
270
271/* -----------------------------------------------------------------------------
272 * Board specific
273 * -----------------------------------------------------------------------------
274 */
275#define CONFIG_SYS_NO_FLASH
276
277/* Uncomment to define the board revision statically */
278/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
279
Aneesh V8e408522011-11-21 23:38:59 +0000280#define CONFIG_SYS_CACHELINE_SIZE 64
281
Tom Rini673283f2011-11-18 12:48:09 +0000282/* Defines for SPL */
283#define CONFIG_SPL
284#define CONFIG_SPL_TEXT_BASE 0x40200800
285#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */
286#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
287
288#define CONFIG_SPL_BSS_START_ADDR 0x80000000
289#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
290
291#define CONFIG_SPL_LIBCOMMON_SUPPORT
292#define CONFIG_SPL_LIBDISK_SUPPORT
293#define CONFIG_SPL_I2C_SUPPORT
294#define CONFIG_SPL_LIBGENERIC_SUPPORT
295#define CONFIG_SPL_SERIAL_SUPPORT
296#define CONFIG_SPL_POWER_SUPPORT
297#define CONFIG_SPL_OMAP3_ID_NAND
298#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
299
300/*
301 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
302 * 64 bytes before this address should be set aside for u-boot.img's
303 * header. That is 0x800FFFC0--0x80100000 should not be used for any
304 * other needs.
305 */
306#define CONFIG_SYS_TEXT_BASE 0x80100000
307#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
308#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
309
Sanjeev Premi39708842011-10-25 06:11:30 +0000310#endif /* __OMAP3_EVM_COMMON_H */