| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 1 | if TEGRA124 |
| 2 | |
| 3 | choice |
| 4 | prompt "Tegra124 board select" |
| Joe Hershberger | a26cd04 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 5 | optional |
| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 6 | |
| Marcel Ziswiler | f38f5f4 | 2017-04-01 15:43:16 -0700 | [diff] [blame] | 7 | config TARGET_APALIS_TK1 |
| 8 | bool "Toradex Apalis TK1 module" |
| Michal Simek | 58008cb | 2018-07-23 15:55:15 +0200 | [diff] [blame] | 9 | select ARCH_SUPPORT_PSCI |
| Marcel Ziswiler | f38f5f4 | 2017-04-01 15:43:16 -0700 | [diff] [blame] | 10 | select CPU_V7_HAS_NONSEC |
| 11 | select CPU_V7_HAS_VIRT |
| Marcel Ziswiler | f38f5f4 | 2017-04-01 15:43:16 -0700 | [diff] [blame] | 12 | |
| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 13 | config TARGET_JETSON_TK1 |
| 14 | bool "NVIDIA Tegra124 Jetson TK1 board" |
| Michal Simek | 58008cb | 2018-07-23 15:55:15 +0200 | [diff] [blame] | 15 | select ARCH_SUPPORT_PSCI |
| Tom Rini | e5ec481 | 2017-01-22 19:43:11 -0500 | [diff] [blame] | 16 | select BOARD_LATE_INIT |
| Masahiro Yamada | 55a65e6 | 2016-08-30 16:22:20 +0900 | [diff] [blame] | 17 | select CPU_V7_HAS_NONSEC |
| 18 | select CPU_V7_HAS_VIRT |
| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 19 | |
| Peter Chubb | b615267 | 2016-08-30 22:54:46 +0000 | [diff] [blame] | 20 | config TARGET_CEI_TK1_SOM |
| 21 | bool "Colorado Engineering Inc Tegra124 TK1-som board" |
| Patrick Delaunay | 4f5128f | 2020-06-18 09:41:34 +0200 | [diff] [blame] | 22 | select ARCH_SUPPORT_PSCI |
| Tom Rini | e5ec481 | 2017-01-22 19:43:11 -0500 | [diff] [blame] | 23 | select BOARD_LATE_INIT |
| Peter Chubb | b615267 | 2016-08-30 22:54:46 +0000 | [diff] [blame] | 24 | select CPU_V7_HAS_NONSEC if !SPL_BUILD |
| 25 | select CPU_V7_HAS_VIRT if !SPL_BUILD |
| 26 | help |
| 27 | The Colorado Engineering Tegra TK1-SOM is a very compact |
| 28 | (51mmx58mm) board that is functionally almost the same as |
| 29 | the Jetson TK1. The main differences are in which balls on |
| 30 | the SoC are assigned to which functions, and the PCIEe |
| 31 | configuration. |
| 32 | |
| Allen Martin | a6c7b46 | 2014-12-04 06:36:30 -0700 | [diff] [blame] | 33 | config TARGET_NYAN_BIG |
| Simon Glass | f374662 | 2015-06-05 14:39:45 -0600 | [diff] [blame] | 34 | bool "Google/NVIDIA Nyan-big Chromebook" |
| Tom Rini | e5ec481 | 2017-01-22 19:43:11 -0500 | [diff] [blame] | 35 | select BOARD_LATE_INIT |
| Allen Martin | a6c7b46 | 2014-12-04 06:36:30 -0700 | [diff] [blame] | 36 | help |
| 37 | Nyan Big is a Tegra124 clamshell board that is very similar |
| 38 | to venice2, but it has a different panel, the sdcard CD and WP |
| 39 | sense are flipped, and it has a different revision of the AS3722 |
| 40 | PMIC. The retail name is the Acer Chromebook 13 CB5-311-T7NN |
| 41 | (13.3-inch HD, NVIDIA Tegra K1, 2GB). |
| 42 | |
| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 43 | config TARGET_VENICE2 |
| 44 | bool "NVIDIA Tegra124 Venice2" |
| Tom Rini | e5ec481 | 2017-01-22 19:43:11 -0500 | [diff] [blame] | 45 | select BOARD_LATE_INIT |
| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 46 | |
| 47 | endchoice |
| 48 | |
| 49 | config SYS_SOC |
| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 50 | default "tegra124" |
| 51 | |
| Peter Chubb | b615267 | 2016-08-30 22:54:46 +0000 | [diff] [blame] | 52 | source "board/cei/cei-tk1-som/Kconfig" |
| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 53 | source "board/nvidia/jetson-tk1/Kconfig" |
| Allen Martin | a6c7b46 | 2014-12-04 06:36:30 -0700 | [diff] [blame] | 54 | source "board/nvidia/nyan-big/Kconfig" |
| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 55 | source "board/nvidia/venice2/Kconfig" |
| Marcel Ziswiler | f38f5f4 | 2017-04-01 15:43:16 -0700 | [diff] [blame] | 56 | source "board/toradex/apalis-tk1/Kconfig" |
| Masahiro Yamada | ddd960e | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 57 | |
| 58 | endif |