| Bin Meng | 9c7dea6 | 2015-05-25 22:35:04 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ARCH_IRQ_H_ |
| 8 | #define _ARCH_IRQ_H_ |
| 9 | |
| 10 | #include <dt-bindings/interrupt-router/intel-irq.h> |
| 11 | |
| 12 | /** |
| 13 | * Intel interrupt router configuration mechanism |
| 14 | * |
| 15 | * There are two known ways of Intel interrupt router configuration mechanism |
| 16 | * so far. On most cases, the IRQ routing configuraiton is controlled by PCI |
| 17 | * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). |
| 18 | * On some newer platforms like BayTrail and Braswell, the IRQ routing is now |
| 19 | * in the IBASE register block where IBASE is memory-mapped. |
| 20 | */ |
| 21 | enum pirq_config { |
| 22 | PIRQ_VIA_PCI, |
| 23 | PIRQ_VIA_IBASE |
| 24 | }; |
| 25 | |
| 26 | /** |
| 27 | * Intel interrupt router control block |
| 28 | * |
| 29 | * Its members' value will be filled in based on device tree's input. |
| 30 | * |
| 31 | * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE |
| 32 | * @link_base: link value base number |
| 33 | * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means |
| 34 | * IRQ N is available to be routed |
| 35 | * @lb_bdf: irq router's PCI bus/device/function number encoding |
| 36 | * @ibase: IBASE register block base address |
| 37 | */ |
| 38 | struct irq_router { |
| 39 | int config; |
| 40 | u32 link_base; |
| 41 | u16 irq_mask; |
| 42 | u32 bdf; |
| 43 | u32 ibase; |
| 44 | }; |
| 45 | |
| 46 | struct pirq_routing { |
| 47 | int bdf; |
| 48 | int pin; |
| 49 | int pirq; |
| 50 | }; |
| 51 | |
| 52 | /* PIRQ link number and value conversion */ |
| 53 | #define LINK_V2N(link, base) (link - base) |
| 54 | #define LINK_N2V(link, base) (link + base) |
| 55 | |
| 56 | #define PIRQ_BITMAP 0xdef8 |
| 57 | |
| 58 | /** |
| 59 | * cpu_irq_init() - Initialize CPU IRQ routing |
| 60 | * |
| 61 | * This initializes some platform-specific registers related to IRQ routing, |
| 62 | * like configuring internal PCI devices to use which PCI interrupt pin, |
| 63 | * and which PCI interrupt pin is mapped to which PIRQ line. Note on some |
| 64 | * platforms, such IRQ routing might be hard-coded thus cannot configure. |
| 65 | */ |
| 66 | void cpu_irq_init(void); |
| 67 | |
| 68 | /** |
| 69 | * pirq_init() - Initialize platform PIRQ routing |
| 70 | * |
| 71 | * This initializes the PIRQ routing on the platform and configures all PCI |
| 72 | * devices' interrupt line register to a working IRQ number on the 8259 PIC. |
| 73 | */ |
| 74 | void pirq_init(void); |
| 75 | |
| 76 | #endif /* _ARCH_IRQ_H_ */ |