blob: 0a86e83fbf45aeee82bb327315206659db309113 [file] [log] [blame]
Aubrey Li26bf7de2007-03-19 01:24:52 +08001/*
2 * U-boot - Configuration file for BF537 STAMP board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF537_STAMP_H__
6#define __CONFIG_BF537_STAMP_H__
Aubrey Li26bf7de2007-03-19 01:24:52 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey Li26bf7de2007-03-19 01:24:52 +080010
11/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040012 * Processor Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +080013 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040014#define CONFIG_BFIN_CPU bf537-0.2
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 20
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
Mike Frysingerf82caac2008-12-08 16:16:11 -050039#define CONFIG_SCLK_DIV 4
Mike Frysingercf6f4692008-06-01 09:09:48 -040040
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x306
49#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
50
51#define CONFIG_EBIU_AMGCTL_VAL 0xFF
52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
54
Mike Frysinger6f5fd562009-01-21 20:47:12 -050055#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Mike Frysingercf6f4692008-06-01 09:09:48 -040056#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
57
Aubrey Li26bf7de2007-03-19 01:24:52 +080058
59/*
60 * Network Settings
61 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040062#ifndef __ADSPBF534__
63#define ADI_CMDS_NETWORK 1
64#define CONFIG_BFIN_MAC
Aubrey Li26bf7de2007-03-19 01:24:52 +080065#define CONFIG_NETCONSOLE 1
66#define CONFIG_NET_MULTI 1
Mike Frysingercf6f4692008-06-01 09:09:48 -040067#endif
68#define CONFIG_HOSTNAME bf537-stamp
69/* Uncomment next line to use fixed MAC address */
70/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
Jon Loeliger079a1362007-07-10 10:12:10 -050071
72
73/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040074 * Flash Settings
Jon Loeligerba2351f2007-07-04 22:31:49 -050075 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040076#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040078#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_FLASH_PROTECTION
80#define CONFIG_SYS_MAX_FLASH_BANKS 1
Mike Frysingercf6f4692008-06-01 09:09:48 -040081/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
82#define CONFIG_SYS_MAX_FLASH_SECT 71
Aubrey Li26bf7de2007-03-19 01:24:52 +080083
Aubrey Li26bf7de2007-03-19 01:24:52 +080084
Mike Frysingercf6f4692008-06-01 09:09:48 -040085/*
86 * SPI Settings
87 */
88#define CONFIG_BFIN_SPI
89#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -040090#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040091#define CONFIG_SPI_FLASH
92#define CONFIG_SPI_FLASH_ATMEL
93#define CONFIG_SPI_FLASH_SPANSION
94#define CONFIG_SPI_FLASH_STMICRO
95#define CONFIG_SPI_FLASH_WINBOND
96
97
98/*
99 * Env Storage Settings
100 */
Mike Frysinger9171fc82008-03-30 15:46:13 -0400101#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysingercf6f4692008-06-01 09:09:48 -0400102#define CONFIG_ENV_IS_IN_SPI_FLASH
Vivi Libc43a8d2009-06-12 10:53:22 +0000103#define CONFIG_ENV_OFFSET 0x10000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200104#define CONFIG_ENV_SIZE 0x2000
Vivi Libc43a8d2009-06-12 10:53:22 +0000105#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400106#else
107#define CONFIG_ENV_IS_IN_FLASH
108#define CONFIG_ENV_OFFSET 0x4000
109#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
110#define CONFIG_ENV_SIZE 0x2000
111#define CONFIG_ENV_SECT_SIZE 0x2000
112#endif
113#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800114#define ENV_IS_EMBEDDED
Mike Frysingercf6f4692008-06-01 09:09:48 -0400115#else
116#define ENV_IS_EMBEDDED_CUSTOM
117#endif
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400118#ifdef ENV_IS_EMBEDDED
119/* WARNING - the following is hand-optimized to fit within
120 * the sector before the environment sector. If it throws
121 * an error during compilation remove an object here to get
122 * it linked after the configuration sector.
123 */
124# define LDS_BOARD_TEXT \
125 cpu/blackfin/traps.o (.text .text.*); \
126 cpu/blackfin/interrupt.o (.text .text.*); \
127 cpu/blackfin/serial.o (.text .text.*); \
128 common/dlmalloc.o (.text .text.*); \
129 lib_generic/crc32.o (.text .text.*); \
130 . = DEFINED(env_offset) ? env_offset : .; \
131 common/env_embedded.o (.text .text.*);
132#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800133
Aubrey Li26bf7de2007-03-19 01:24:52 +0800134
135/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400136 * I2C Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +0800137 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400138#define CONFIG_BFIN_TWI_I2C 1
139#define CONFIG_HARD_I2C 1
140#define CONFIG_SYS_I2C_SPEED 50000
141#define CONFIG_SYS_I2C_SLAVE 0
Aubrey Li26bf7de2007-03-19 01:24:52 +0800142
Aubrey Li26bf7de2007-03-19 01:24:52 +0800143
144/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400145 * SPI_MMC Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +0800146 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400147#define CONFIG_MMC
148#define CONFIG_BFIN_SPI_MMC
149
150
151/*
152 * NAND Settings
153 */
154/* #define CONFIG_BF537_NAND */
155#ifdef CONFIG_BF537_NAND
156# define CONFIG_CMD_NAND
157#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_NAND_ADDR 0x20212000
160#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_ADDR
161#define CONFIG_SYS_MAX_NAND_DEVICE 1
Aubrey Li26bf7de2007-03-19 01:24:52 +0800162#define SECTORSIZE 512
163#define ADDR_COLUMN 1
164#define ADDR_PAGE 2
165#define ADDR_COLUMN_PAGE 3
166#define NAND_ChipID_UNKNOWN 0x00
167#define NAND_MAX_FLOORS 1
Aubrey Li26bf7de2007-03-19 01:24:52 +0800168#define BFIN_NAND_READY PF3
169
Mike Frysingercf6f4692008-06-01 09:09:48 -0400170#define NAND_WAIT_READY(nand) \
171 do { \
172 int timeout = 0; \
173 while (!(*pPORTFIO & PF3)) \
174 if (timeout++ > 100000) \
175 break; \
Aubrey Li26bf7de2007-03-19 01:24:52 +0800176 } while (0)
177
Mike Frysingercf6f4692008-06-01 09:09:48 -0400178#define BFIN_NAND_CLE (1 << 2) /* A2 -> Command Enable */
179#define BFIN_NAND_ALE (1 << 1) /* A1 -> Address Enable */
180#define WRITE_NAND_COMMAND(d, adr) bfin_write8(adr | BFIN_NAND_CLE, d)
181#define WRITE_NAND_ADDRESS(d, adr) bfin_write8(adr | BFIN_NAND_ALE, d)
182#define WRITE_NAND(d, adr) bfin_write8(adr, d)
183#define READ_NAND(adr) bfin_read8(adr)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800184
Aubrey Li26bf7de2007-03-19 01:24:52 +0800185
186/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400187 * CF-CARD IDE-HDD Support
Aubrey Li26bf7de2007-03-19 01:24:52 +0800188 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400189/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
190/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
191/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800192
Mike Frysingercf6f4692008-06-01 09:09:48 -0400193#if defined(CONFIG_BFIN_CF_IDE) || \
194 defined(CONFIG_BFIN_HDD_IDE) || \
195 defined(CONFIG_BFIN_TRUE_IDE)
196# define CONFIG_BFIN_IDE 1
197# define CONFIG_CMD_IDE
198#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800199
Aubrey Li26bf7de2007-03-19 01:24:52 +0800200#if defined(CONFIG_BFIN_IDE)
201
202#define CONFIG_DOS_PARTITION 1
203/*
204 * IDE/ATA stuff
205 */
206#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
207#undef CONFIG_IDE_LED /* no led for ide supported */
208#undef CONFIG_IDE_RESET /* no reset for ide supported */
209
Mike Frysingercf6f4692008-06-01 09:09:48 -0400210#define CONFIG_SYS_IDE_MAXBUS 1
211#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800212
Mike Frysingercf6f4692008-06-01 09:09:48 -0400213#undef CONFIG_EBIU_AMBCTL1_VAL
214#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
Aubrey Li26bf7de2007-03-19 01:24:52 +0800215
216#define CONFIG_CF_ATASEL_DIS 0x20311800
217#define CONFIG_CF_ATASEL_ENA 0x20311802
218
219#if defined(CONFIG_BFIN_TRUE_IDE)
220/*
221 * Note that these settings aren't for the most part used in include/ata.h
222 * when all of the ATA registers are setup
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
225#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400226#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
227#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
228#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800230
Mike Frysingercf6f4692008-06-01 09:09:48 -0400231#elif defined(CONFIG_BFIN_CF_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
233#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400234#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
235#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
236#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800238
Mike Frysingercf6f4692008-06-01 09:09:48 -0400239#elif defined(CONFIG_BFIN_HDD_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
241#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400242#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
243#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
244#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800246#undef CONFIG_SCLK_DIV
247#define CONFIG_SCLK_DIV 8
Mike Frysingercf6f4692008-06-01 09:09:48 -0400248#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800249
Mike Frysingercf6f4692008-06-01 09:09:48 -0400250#endif
251
252
253/*
254 * Misc Settings
255 */
256#define CONFIG_MISC_INIT_R
257#define CONFIG_RTC_BFIN
258#define CONFIG_UART_CONSOLE 0
259
260/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
261
262/* Define if want to do post memory test */
263#undef CONFIG_POST
264#ifdef CONFIG_POST
265#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
266#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
267#endif
268
269
270/*
271 * Pull in common ADI header for remaining command/environment setup
272 */
273#include <configs/bfin_adi_common.h>
Aubrey Li26bf7de2007-03-19 01:24:52 +0800274
Aubrey Li26bf7de2007-03-19 01:24:52 +0800275#endif