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wdenkf8cac652002-08-26 22:36:39 +00001/*
2 * (C) Copyright 2001
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2001-2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <malloc.h>
29#include <mpc8xx.h>
30
31/* ------------------------------------------------------------------------- */
32
33static long int dram_size (long int, long int *, long int);
34
35/* ------------------------------------------------------------------------- */
36
37#define _NOT_USED_ 0xFFFFFFFF
38
39const uint sdram_table[] =
40{
41#if (MPC8XX_SPEED <= 50000000L)
42 /*
43 * Single Read. (Offset 0 in UPMA RAM)
44 */
45 0x0F07EC04,
46 0x01BBD804,
47 0x1FF7F440,
48 0xFFFFFC07,
49 0xFFFFFFFF,
50
51 /*
52 * SDRAM Initialization (offset 5 in UPMA RAM)
53 *
54 * This is no UPM entry point. The following definition uses
55 * the remaining space to establish an initialization
56 * sequence, which is executed by a RUN command.
57 *
58 */
59 0x1FE7F434,
60 0xEFABE834,
61 0x1FA7D435,
62
63 /*
64 * Burst Read. (Offset 8 in UPMA RAM)
65 */
66 0x0F07EC04,
67 0x10EFDC04,
68 0xF0AFFC00,
69 0xF0AFFC00,
70 0xF1AFFC00,
71 0xFFAFFC40,
72 0xFFAFFC07,
73 0xFFFFFFFF,
74 0xFFFFFFFF,
75 0xFFFFFFFF,
76 0xFFFFFFFF,
77 0xFFFFFFFF,
78 0xFFFFFFFF,
79 0xFFFFFFFF,
80 0xFFFFFFFF,
81 0xFFFFFFFF,
82
83 /*
84 * Single Write. (Offset 18 in UPMA RAM)
85 */
86 0x0E07E804,
87 0x01BBD000,
88 0x1FF7F447,
89 0xFFFFFFFF,
90 0xFFFFFFFF,
91 0xFFFFFFFF,
92 0xFFFFFFFF,
93 0xFFFFFFFF,
94
95 /*
96 * Burst Write. (Offset 20 in UPMA RAM)
97 */
98 0x0E07E800,
99 0x10EFD400,
100 0xF0AFFC00,
101 0xF0AFFC00,
102 0xF1AFFC47,
103 0xFFFFFFFF,
104 0xFFFFFFFF,
105 0xFFFFFFFF,
106 0xFFFFFFFF,
107 0xFFFFFFFF,
108 0xFFFFFFFF,
109 0xFFFFFFFF,
110 0xFFFFFFFF,
111 0xFFFFFFFF,
112 0xFFFFFFFF,
113 0xFFFFFFFF,
114
115 /*
116 * Refresh (Offset 30 in UPMA RAM)
117 */
118 0x1FF7DC84,
119 0xFFFFFC04,
120 0xFFFFFC84,
121 0xFFFFFC07,
122 0xFFFFFFFF,
123 0xFFFFFFFF,
124 0xFFFFFFFF,
125 0xFFFFFFFF,
126 0xFFFFFFFF,
127 0xFFFFFFFF,
128 0xFFFFFFFF,
129 0xFFFFFFFF,
130
131 /*
132 * Exception. (Offset 3c in UPMA RAM)
133 */
134 0x7FFFFC07,
135 0xFFFFFFFF,
136 0xFFFFFFFF,
137 0xFFFFFFFF
138
139#else
140
141 /*
142 * Single Read. (Offset 0 in UPMA RAM)
143 */
144 0x1F07FC04,
145 0xEEAFEC04,
146 0x11AFDC04,
147 0xEFBBF800,
148 0x1FF7F447,
149
150 /*
151 * SDRAM Initialization (offset 5 in UPMA RAM)
152 *
153 * This is no UPM entry point. The following definition uses
154 * the remaining space to establish an initialization
155 * sequence, which is executed by a RUN command.
156 *
157 */
158 0x1FF7F434,
159 0xEFEBE834,
160 0x1FB7D435,
161
162 /*
163 * Burst Read. (Offset 8 in UPMA RAM)
164 */
165 0x1F07FC04,
166 0xEEAFEC04,
167 0x10AFDC04,
168 0xF0AFFC00,
169 0xF0AFFC00,
170 0xF1AFFC00,
171 0xEFBBF800,
172 0x1FF7F447,
173 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
174 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
175
176 /*
177 * Single Write. (Offset 18 in UPMA RAM)
178 */
179 0x1F07FC04,
180 0xEEAFE800,
181 0x01BBD004,
182 0x1FF7F447,
183 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
184
185 /*
186 * Burst Write. (Offset 20 in UPMA RAM)
187 */
188 0x1F07FC04,
189 0xEEAFE800,
190 0x10AFD400,
191 0xF0AFFC00,
192 0xF0AFFC00,
193 0xE1BBF804,
194 0x1FF7F447,
195 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
196 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
197
198 /*
199 * Refresh (Offset 30 in UPMA RAM)
200 */
201 0x1FF7DC84,
202 0xFFFFFC04,
203 0xFFFFFC04,
204 0xFFFFFC04,
205 0xFFFFFC84,
206 0xFFFFFC07,
207 _NOT_USED_, _NOT_USED_, _NOT_USED_,
208 _NOT_USED_, _NOT_USED_, _NOT_USED_,
209
210 /*
211 * Exception. (Offset 3c in UPMA RAM)
212 */
213 0x7FFFFC07, /* last */
214 _NOT_USED_, _NOT_USED_, _NOT_USED_,
215#endif
216};
217
218/* ------------------------------------------------------------------------- */
219
220
221/*
222 * Check Board Identity:
223 *
224 */
225
226int checkboard (void)
227{
228 printf ("Board: Nexus NX823");
229 return (0);
230}
231
232/* ------------------------------------------------------------------------- */
233
234long int initdram (int board_type)
235{
236 volatile immap_t *immap = (immap_t *)CFG_IMMR;
237 volatile memctl8xx_t *memctl = &immap->im_memctl;
238 long int size_b0, size_b1, size8, size9;
239
240 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
241
242 /*
243 * Up to 2 Banks of 64Mbit x 2 devices
244 * Initial builds only have 1
245 */
246 memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
247 memctl->memc_mar = 0x00000088;
248
249 /*
250 * Map controller SDRAM bank 0
251 */
252 memctl->memc_or1 = CFG_OR1_PRELIM;
253 memctl->memc_br1 = CFG_BR1_PRELIM;
254 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
255 udelay(200);
256
257 /*
258 * Map controller SDRAM bank 1
259 */
260 memctl->memc_or2 = CFG_OR2_PRELIM;
261 memctl->memc_br2 = CFG_BR2_PRELIM;
262
263 /*
264 * Perform SDRAM initializsation sequence
265 */
266 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
267 udelay(1);
268 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
269 udelay(1);
270
271 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
272 udelay(1);
273 memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
274 udelay(1);
275
276 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
277 udelay (1000);
278
279 /*
280 * Preliminary prescaler for refresh (depends on number of
281 * banks): This value is selected for four cycles every 62.4 us
282 * with two SDRAM banks or four cycles every 31.2 us with one
283 * bank. It will be adjusted after memory sizing.
284 */
285 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
286
287 memctl->memc_mar = 0x00000088;
288
289
290 /*
291 * Check Bank 0 Memory Size for re-configuration
292 *
293 * try 8 column mode
294 */
295 size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
296
297 udelay (1000);
298
299 /*
300 * try 9 column mode
301 */
302 size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
303
304 if (size8 < size9) { /* leave configuration at 9 columns */
305 size_b0 = size9;
306/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
307 } else { /* back to 8 columns */
308 size_b0 = size8;
309 memctl->memc_mamr = CFG_MAMR_8COL;
310 udelay(500);
311/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
312 }
313
314 /*
315 * Check Bank 1 Memory Size
316 * use current column settings
317 * [9 column SDRAM may also be used in 8 column mode,
318 * but then only half the real size will be used.]
319 */
320 size_b1 = dram_size (memctl->memc_mamr, (ulong *)SDRAM_BASE2_PRELIM,
321 SDRAM_MAX_SIZE);
322/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
323
324 udelay (1000);
325
326 /*
327 * Adjust refresh rate depending on SDRAM type, both banks
328 * For types > 128 MBit leave it at the current (fast) rate
329 */
330 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
331 /* reduce to 15.6 us (62.4 us / quad) */
332 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
333 udelay(1000);
334 }
335
336 /*
337 * Final mapping: map bigger bank first
338 */
339 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
340
341 memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
342 memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
343
344 if (size_b0 > 0) {
345 /*
346 * Position Bank 0 immediately above Bank 1
347 */
348 memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
349 memctl->memc_br1 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
350 + size_b1;
351 } else {
352 unsigned long reg;
353 /*
354 * No bank 0
355 *
356 * invalidate bank
357 */
358 memctl->memc_br1 = 0;
359
360 /* adjust refresh rate depending on SDRAM type, one bank */
361 reg = memctl->memc_mptpr;
362 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
363 memctl->memc_mptpr = reg;
364 }
365
366 } else { /* SDRAM Bank 0 is bigger - map first */
367
368 memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
369 memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
370
371 if (size_b1 > 0) {
372 /*
373 * Position Bank 1 immediately above Bank 0
374 */
375 memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
376 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
377 + size_b0;
378 } else {
379 unsigned long reg;
380 /*
381 * No bank 1
382 *
383 * invalidate bank
384 */
385 memctl->memc_br2 = 0;
386
387 /* adjust refresh rate depending on SDRAM type, one bank */
388 reg = memctl->memc_mptpr;
389 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
390 memctl->memc_mptpr = reg;
391 }
392 }
393
394 udelay(10000);
395
396 return (size_b0 + size_b1);
397}
398
399/* ------------------------------------------------------------------------- */
400
401/*
402 * Check memory range for valid RAM. A simple memory test determines
403 * the actually available RAM size between addresses `base' and
404 * `base + maxsize'. Some (not all) hardware errors are detected:
405 * - short between address lines
406 * - short between data lines
407 */
408
409static long int dram_size (long int mamr_value, long int *base, long int maxsize)
410{
411 volatile immap_t *immap = (immap_t *)CFG_IMMR;
412 volatile memctl8xx_t *memctl = &immap->im_memctl;
413 volatile long int *addr;
414 long int cnt, val;
415
416 memctl->memc_mamr = mamr_value;
417
418 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
419 addr = base + cnt; /* pointer arith! */
420
421 *addr = ~cnt;
422 }
423
424 /* write 0 to base address */
425 addr = base;
426 *addr = 0;
427
428 /* check at base address */
429 if ((val = *addr) != 0) {
430 return (0);
431 }
432
433 for (cnt = 1; ; cnt <<= 1) {
434 addr = base + cnt; /* pointer arith! */
435
436 val = *addr;
437
438 if (val != (~cnt)) {
439 return (cnt * sizeof(long));
440 }
441 }
442 /* NOTREACHED */
443}
444
445u_long *my_sernum;
446
447int misc_init_r (void)
448{
449 DECLARE_GLOBAL_DATA_PTR;
450
451 char tmp[50];
452 u_char *e = gd->bd->bi_enetaddr;
453
454 /* save serial numbre from flash (uniquely programmed) */
455 my_sernum = malloc(8);
456 memcpy(my_sernum,gd->bd->bi_sernum,8);
457
458 /* save env variables according to sernum */
459 sprintf(tmp,"%08lx%08lx",my_sernum[0],my_sernum[1]);
460 setenv("serial#",tmp);
461
462 sprintf(tmp,"%02x:%02x:%02x:%02x:%02x:%02x"
463 ,e[0],e[1],e[2],e[3],e[4],e[5]);
464 setenv("ethaddr",tmp);
465 return (0);
466}
467
468void load_sernum_ethaddr (void)
469{
470 DECLARE_GLOBAL_DATA_PTR;
471
472 int i;
473 bd_t * bd = gd->bd;
474
475 for (i = 0; i < 8; i++) {
476 bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i);
477 }
478 bd->bi_enetaddr[0] = 0x10;
479 bd->bi_enetaddr[1] = 0x20;
480 bd->bi_enetaddr[2] = 0x30;
481 bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
482 bd->bi_enetaddr[4] = bd->bi_sernum[5];
483 bd->bi_enetaddr[5] = bd->bi_sernum[6];
484}
485