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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 51855e8981e1b5e0a7b919662c32d0e4a374f575 / . / board / amcc / sequoia / sdram.c
blob: ea987179e74c2d640ff4be314e5e76bd261c9da7 [file] [log] [blame]
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1/*
2 * (C) Copyright 2006
Stefan Roese02388982007-01-05 10:38:05 +0100[diff] [blame]3 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
4 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
5 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
6 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
7 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
8 *
Stefan Roese07b7b002007-03-06 07:47:04 +0100[diff] [blame]9 * (C) Copyright 2006-2007
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]10 * Stefan Roese, DENX Software Engineering, sr@denx.de.
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]12 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]13 */
14
Stefan Roese02388982007-01-05 10:38:05 +0100[diff] [blame]15/* define DEBUG for debug output */
16#undef DEBUG
17
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]18#include <common.h>
19#include <asm/processor.h>
Stefan Roese02388982007-01-05 10:38:05 +0100[diff] [blame]20#include <asm/io.h>
Stefan Roeseb36df562010-09-09 19:18:00 +0200[diff] [blame]21#include <asm/ppc440.h>
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]22
Simon Glass088454c2017-03-31 08:40:25 -0600[diff] [blame]23DECLARE_GLOBAL_DATA_PTR;
24
Stefan Roese02388982007-01-05 10:38:05 +0100[diff] [blame]25/*-----------------------------------------------------------------------------+
Larry Johnsonce3902e2007-12-30 01:00:50 -0500[diff] [blame]26 * Prototypes
27 *-----------------------------------------------------------------------------*/
28extern int denali_wait_for_dlllock(void);
29extern void denali_core_search_data_eye(void);
Stefan Roese02388982007-01-05 10:38:05 +0100[diff] [blame]30
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]31/*************************************************************************
32 *
Simon Glassf1683aa2017-04-06 12:47:05 -0600[diff] [blame]33 * dram_init -- 440EPx's DDR controller is a DENALI Core
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]34 *
35 ************************************************************************/
Simon Glassf1683aa2017-04-06 12:47:05 -0600[diff] [blame]36int dram_init(void)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]37{
Stefan Roese345b77b2014-03-04 15:34:35 +0100[diff] [blame]38#if !defined(CONFIG_SYS_RAMBOOT)
Stefan Roese07b7b002007-03-06 07:47:04 +0100[diff] [blame]39 ulong speed = get_bus_freq(0);
40
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]41 mtsdram(DDR0_02, 0x00000000);
42
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]43 mtsdram(DDR0_00, 0x0000190A);
44 mtsdram(DDR0_01, 0x01000000);
45 mtsdram(DDR0_03, 0x02030602);
Stefan Roese07b7b002007-03-06 07:47:04 +0100[diff] [blame]46 mtsdram(DDR0_04, 0x0A020200);
47 mtsdram(DDR0_05, 0x02020308);
48 mtsdram(DDR0_06, 0x0102C812);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]49 mtsdram(DDR0_07, 0x000D0100);
Stefan Roese07b7b002007-03-06 07:47:04 +0100[diff] [blame]50 mtsdram(DDR0_08, 0x02430001);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]51 mtsdram(DDR0_09, 0x00011D5F);
Mikhail Zolotaryovee86fd12009-03-11 10:54:46 +0200[diff] [blame]52 mtsdram(DDR0_10, 0x00000100);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]53 mtsdram(DDR0_11, 0x0027C800);
54 mtsdram(DDR0_12, 0x00000003);
55 mtsdram(DDR0_14, 0x00000000);
56 mtsdram(DDR0_17, 0x19000000);
57 mtsdram(DDR0_18, 0x19191919);
58 mtsdram(DDR0_19, 0x19191919);
59 mtsdram(DDR0_20, 0x0B0B0B0B);
60 mtsdram(DDR0_21, 0x0B0B0B0B);
61 mtsdram(DDR0_22, 0x00267F0B);
62 mtsdram(DDR0_23, 0x00000000);
63 mtsdram(DDR0_24, 0x01010002);
Stefan Roesef544ff62007-05-05 08:29:01 +0200[diff] [blame]64 if (speed > 133333334)
Stefan Roese07b7b002007-03-06 07:47:04 +0100[diff] [blame]65 mtsdram(DDR0_26, 0x5B26050C);
66 else
67 mtsdram(DDR0_26, 0x5B260408);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]68 mtsdram(DDR0_27, 0x0000682B);
69 mtsdram(DDR0_28, 0x00000000);
70 mtsdram(DDR0_31, 0x00000000);
71 mtsdram(DDR0_42, 0x01000006);
Stefan Roese07b7b002007-03-06 07:47:04 +0100[diff] [blame]72 mtsdram(DDR0_43, 0x030A0200);
73 mtsdram(DDR0_44, 0x00000003);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]74 mtsdram(DDR0_02, 0x00000001);
75
Larry Johnsonce3902e2007-12-30 01:00:50 -0500[diff] [blame]76 denali_wait_for_dlllock();
Stefan Roese345b77b2014-03-04 15:34:35 +0100[diff] [blame]77#endif /* #ifndef CONFIG_SYS_RAMBOOT */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]78
Stefan Roese02388982007-01-05 10:38:05 +0100[diff] [blame]79#ifdef CONFIG_DDR_DATA_EYE
80 /* -----------------------------------------------------------+
81 * Perform data eye search if requested.
82 * ----------------------------------------------------------*/
Larry Johnsonce3902e2007-12-30 01:00:50 -0500[diff] [blame]83 denali_core_search_data_eye();
Stefan Roese02388982007-01-05 10:38:05 +0100[diff] [blame]84#endif
85
Stefan Roesed5a163d2008-01-11 15:53:58 +0100[diff] [blame]86 /*
87 * Clear possible errors resulting from data-eye-search.
88 * If not done, then we could get an interrupt later on when
89 * exceptions are enabled.
90 */
91 set_mcsr(get_mcsr());
92
Simon Glass088454c2017-03-31 08:40:25 -0600[diff] [blame]93 gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20;
94
95 return 0;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]96}