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Bill Richardson55ae10f2012-10-20 11:44:34 +00001/*
2 * Copyright (c) 2012 The Chromium OS Authors.
Wolfgang Denk1a459662013-07-08 09:37:19 +02003 * SPDX-License-Identifier: GPL-2.0+
Bill Richardson55ae10f2012-10-20 11:44:34 +00004 */
5
6/*
7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8 * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9 * consisting of a standard header and a device-specific set of registers. PCI
10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11 * other things). Within the PCI configuration space, the GPIOBASE register
12 * tells us where in the device's I/O region we can find more registers to
13 * actually access the GPIOs.
14 *
15 * PCI bus/device/function 0:1f:0 => PCI config registers
16 * PCI config register "GPIOBASE"
17 * PCI I/O space + [GPIOBASE] => start of GPIO registers
18 * GPIO registers => gpio pin function, direction, value
Bill Richardson57be9172012-10-20 11:44:36 +000019 *
20 *
21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22 * ICH versions have more, but the decoding the matrix that describes them is
23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24 * but they will ONLY work for certain unspecified chipsets because the offset
25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26 * reserved or subject to arcane restrictions.
Bill Richardson55ae10f2012-10-20 11:44:34 +000027 */
28
29#include <common.h>
Simon Glass74141122014-10-10 07:49:18 -060030#include <dm.h>
31#include <errno.h>
32#include <fdtdec.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000033#include <pci.h>
34#include <asm/gpio.h>
35#include <asm/io.h>
Simon Glass1b4f25f2014-11-12 22:42:24 -070036#include <asm/pci.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000037
Simon Glass74141122014-10-10 07:49:18 -060038#define GPIO_PER_BANK 32
39
Simon Glass74141122014-10-10 07:49:18 -060040struct ich6_bank_priv {
41 /* These are I/O addresses */
Bin Mengb71eec32014-12-17 15:50:38 +080042 uint16_t use_sel;
43 uint16_t io_sel;
44 uint16_t lvl;
Bill Richardson57be9172012-10-20 11:44:36 +000045};
Bill Richardson55ae10f2012-10-20 11:44:34 +000046
Simon Glass1b4f25f2014-11-12 22:42:24 -070047/* TODO: Move this to device tree, or platform data */
48void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
49{
50 gd->arch.gpio_map = map;
51}
Simon Glass1b4f25f2014-11-12 22:42:24 -070052
Simon Glass74141122014-10-10 07:49:18 -060053static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
Bill Richardson57be9172012-10-20 11:44:36 +000054{
Simon Glass74141122014-10-10 07:49:18 -060055 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
56 pci_dev_t pci_dev; /* handle for 0:1f:0 */
Bill Richardson55ae10f2012-10-20 11:44:34 +000057 u8 tmpbyte;
58 u16 tmpword;
59 u32 tmplong;
Bin Mengb71eec32014-12-17 15:50:38 +080060 u16 gpiobase;
Simon Glass74141122014-10-10 07:49:18 -060061 int offset;
Bill Richardson55ae10f2012-10-20 11:44:34 +000062
63 /* Where should it be? */
Simon Glass74141122014-10-10 07:49:18 -060064 pci_dev = PCI_BDF(0, 0x1f, 0);
Bill Richardson55ae10f2012-10-20 11:44:34 +000065
66 /* Is the device present? */
Simon Glass1b4f25f2014-11-12 22:42:24 -070067 tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID);
Bill Richardson55ae10f2012-10-20 11:44:34 +000068 if (tmpword != PCI_VENDOR_ID_INTEL) {
69 debug("%s: wrong VendorID\n", __func__);
Simon Glass74141122014-10-10 07:49:18 -060070 return -ENODEV;
Bill Richardson55ae10f2012-10-20 11:44:34 +000071 }
Bill Richardson57be9172012-10-20 11:44:36 +000072
Simon Glass1b4f25f2014-11-12 22:42:24 -070073 tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID);
Bill Richardson57be9172012-10-20 11:44:36 +000074 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
Bill Richardson55ae10f2012-10-20 11:44:34 +000075 /*
Bill Richardson57be9172012-10-20 11:44:36 +000076 * We'd like to validate the Device ID too, but pretty much any
Bill Richardson55ae10f2012-10-20 11:44:34 +000077 * value is either a) correct with slight differences, or b)
Bill Richardson57be9172012-10-20 11:44:36 +000078 * correct but undocumented. We'll have to check a bunch of other
79 * things instead...
Bill Richardson55ae10f2012-10-20 11:44:34 +000080 */
81
82 /* I/O should already be enabled (it's a RO bit). */
Simon Glass1b4f25f2014-11-12 22:42:24 -070083 tmpword = pci_read_config16(pci_dev, PCI_COMMAND);
Bill Richardson55ae10f2012-10-20 11:44:34 +000084 if (!(tmpword & PCI_COMMAND_IO)) {
85 debug("%s: device IO not enabled\n", __func__);
Simon Glass74141122014-10-10 07:49:18 -060086 return -ENODEV;
Bill Richardson55ae10f2012-10-20 11:44:34 +000087 }
88
89 /* Header Type must be normal (bits 6-0 only; see spec.) */
Simon Glass1b4f25f2014-11-12 22:42:24 -070090 tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE);
Bill Richardson55ae10f2012-10-20 11:44:34 +000091 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
92 debug("%s: invalid Header type\n", __func__);
Simon Glass74141122014-10-10 07:49:18 -060093 return -ENODEV;
Bill Richardson55ae10f2012-10-20 11:44:34 +000094 }
95
96 /* Base Class must be a bridge device */
Simon Glass1b4f25f2014-11-12 22:42:24 -070097 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE);
Bill Richardson55ae10f2012-10-20 11:44:34 +000098 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
99 debug("%s: invalid class\n", __func__);
Simon Glass74141122014-10-10 07:49:18 -0600100 return -ENODEV;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000101 }
102 /* Sub Class must be ISA */
Simon Glass1b4f25f2014-11-12 22:42:24 -0700103 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000104 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
105 debug("%s: invalid subclass\n", __func__);
Simon Glass74141122014-10-10 07:49:18 -0600106 return -ENODEV;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000107 }
108
109 /* Programming Interface must be 0x00 (no others exist) */
Simon Glass1b4f25f2014-11-12 22:42:24 -0700110 tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000111 if (tmpbyte != 0x00) {
112 debug("%s: invalid interface type\n", __func__);
Simon Glass74141122014-10-10 07:49:18 -0600113 return -ENODEV;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000114 }
115
116 /*
117 * GPIOBASE moved to its current offset with ICH6, but prior to
118 * that it was unused (or undocumented). Check that it looks
Bin Mengb71eec32014-12-17 15:50:38 +0800119 * okay: not all ones or zeros.
120 *
121 * Note we don't need check bit0 here, because the Tunnel Creek
122 * GPIO base address register bit0 is reserved (read returns 0),
123 * while on the Ivybridge the bit0 is used to indicate it is an
124 * I/O space.
Bill Richardson55ae10f2012-10-20 11:44:34 +0000125 */
Simon Glass1b4f25f2014-11-12 22:42:24 -0700126 tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
Bin Mengb71eec32014-12-17 15:50:38 +0800127 if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
Bill Richardson55ae10f2012-10-20 11:44:34 +0000128 debug("%s: unexpected GPIOBASE value\n", __func__);
Simon Glass74141122014-10-10 07:49:18 -0600129 return -ENODEV;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000130 }
131
132 /*
133 * Okay, I guess we're looking at the right device. The actual
134 * GPIO registers are in the PCI device's I/O space, starting
135 * at the offset that we just read. Bit 0 indicates that it's
136 * an I/O address, not a memory address, so mask that off.
137 */
Bin Mengb71eec32014-12-17 15:50:38 +0800138 gpiobase = tmplong & 0xfffe;
Simon Glass74141122014-10-10 07:49:18 -0600139 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
140 if (offset == -1) {
141 debug("%s: Invalid register offset %d\n", __func__, offset);
142 return -EINVAL;
143 }
144 plat->base_addr = gpiobase + offset;
145 plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
146 "bank-name", NULL);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000147
Bill Richardson55ae10f2012-10-20 11:44:34 +0000148 return 0;
149}
150
Simon Glass1b4f25f2014-11-12 22:42:24 -0700151static int ich6_gpio_probe(struct udevice *dev)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000152{
Simon Glass74141122014-10-10 07:49:18 -0600153 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
154 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
155 struct ich6_bank_priv *bank = dev_get_priv(dev);
156
Simon Glass1b4f25f2014-11-12 22:42:24 -0700157 if (gd->arch.gpio_map) {
Bin Meng27955732014-12-12 21:05:23 +0800158 setup_pch_gpios(plat->base_addr, gd->arch.gpio_map);
Simon Glass1b4f25f2014-11-12 22:42:24 -0700159 gd->arch.gpio_map = NULL;
160 }
Bin Meng27955732014-12-12 21:05:23 +0800161
Simon Glass74141122014-10-10 07:49:18 -0600162 uc_priv->gpio_count = GPIO_PER_BANK;
163 uc_priv->bank_name = plat->bank_name;
164 bank->use_sel = plat->base_addr;
165 bank->io_sel = plat->base_addr + 4;
166 bank->lvl = plat->base_addr + 8;
167
168 return 0;
169}
170
Simon Glass1b4f25f2014-11-12 22:42:24 -0700171static int ich6_gpio_request(struct udevice *dev, unsigned offset,
172 const char *label)
Simon Glass74141122014-10-10 07:49:18 -0600173{
174 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000175 u32 tmplong;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000176
177 /*
178 * Make sure that the GPIO pin we want isn't already in use for some
179 * built-in hardware function. We have to check this for every
180 * requested pin.
181 */
Simon Glass74141122014-10-10 07:49:18 -0600182 tmplong = inl(bank->use_sel);
183 if (!(tmplong & (1UL << offset))) {
Bill Richardson57be9172012-10-20 11:44:36 +0000184 debug("%s: gpio %d is reserved for internal use\n", __func__,
Simon Glass74141122014-10-10 07:49:18 -0600185 offset);
186 return -EPERM;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000187 }
188
Bill Richardson55ae10f2012-10-20 11:44:34 +0000189 return 0;
190}
191
Simon Glass74141122014-10-10 07:49:18 -0600192static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000193{
Simon Glass74141122014-10-10 07:49:18 -0600194 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson57be9172012-10-20 11:44:36 +0000195 u32 tmplong;
Bill Richardson57be9172012-10-20 11:44:36 +0000196
Simon Glass74141122014-10-10 07:49:18 -0600197 tmplong = inl(bank->io_sel);
198 tmplong |= (1UL << offset);
199 outl(bank->io_sel, tmplong);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000200 return 0;
201}
202
Simon Glass74141122014-10-10 07:49:18 -0600203static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
204 int value)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000205{
Simon Glass74141122014-10-10 07:49:18 -0600206 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000207 u32 tmplong;
208
Axel Lin0a547452014-12-07 12:48:27 +0800209 gpio_set_value(offset, value);
210
Simon Glass74141122014-10-10 07:49:18 -0600211 tmplong = inl(bank->io_sel);
212 tmplong &= ~(1UL << offset);
213 outl(bank->io_sel, tmplong);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000214 return 0;
215}
216
Simon Glass74141122014-10-10 07:49:18 -0600217static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
218
Bill Richardson55ae10f2012-10-20 11:44:34 +0000219{
Simon Glass74141122014-10-10 07:49:18 -0600220 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000221 u32 tmplong;
Bill Richardson57be9172012-10-20 11:44:36 +0000222 int r;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000223
Simon Glass74141122014-10-10 07:49:18 -0600224 tmplong = inl(bank->lvl);
225 r = (tmplong & (1UL << offset)) ? 1 : 0;
Bill Richardson57be9172012-10-20 11:44:36 +0000226 return r;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000227}
228
Simon Glass74141122014-10-10 07:49:18 -0600229static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
230 int value)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000231{
Simon Glass74141122014-10-10 07:49:18 -0600232 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000233 u32 tmplong;
234
Simon Glass74141122014-10-10 07:49:18 -0600235 tmplong = inl(bank->lvl);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000236 if (value)
Simon Glass74141122014-10-10 07:49:18 -0600237 tmplong |= (1UL << offset);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000238 else
Simon Glass74141122014-10-10 07:49:18 -0600239 tmplong &= ~(1UL << offset);
240 outl(bank->lvl, tmplong);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000241 return 0;
242}
Simon Glass74141122014-10-10 07:49:18 -0600243
244static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
245{
246 struct ich6_bank_priv *bank = dev_get_priv(dev);
247 u32 mask = 1UL << offset;
248
249 if (!(inl(bank->use_sel) & mask))
250 return GPIOF_FUNC;
251 if (inl(bank->io_sel) & mask)
252 return GPIOF_INPUT;
253 else
254 return GPIOF_OUTPUT;
255}
256
257static const struct dm_gpio_ops gpio_ich6_ops = {
258 .request = ich6_gpio_request,
259 .direction_input = ich6_gpio_direction_input,
260 .direction_output = ich6_gpio_direction_output,
261 .get_value = ich6_gpio_get_value,
262 .set_value = ich6_gpio_set_value,
263 .get_function = ich6_gpio_get_function,
264};
265
266static const struct udevice_id intel_ich6_gpio_ids[] = {
267 { .compatible = "intel,ich6-gpio" },
268 { }
269};
270
271U_BOOT_DRIVER(gpio_ich6) = {
272 .name = "gpio_ich6",
273 .id = UCLASS_GPIO,
274 .of_match = intel_ich6_gpio_ids,
275 .ops = &gpio_ich6_ops,
276 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
277 .probe = ich6_gpio_probe,
278 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
279 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
280};