blob: 7992d0ebeebf8ffb0fb86c3bdced2f856e76d67e [file] [log] [blame]
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05301/*
2 * (C) Copyright 2010
3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05306 */
7
8#ifndef _DW_ETH_H
9#define _DW_ETH_H
10
Alexey Brodkin66d027e2016-06-27 13:17:51 +030011#ifdef CONFIG_DM_GPIO
12#include <asm-generic/gpio.h>
13#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010014
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053015#define CONFIG_TX_DESCR_NUM 16
16#define CONFIG_RX_DESCR_NUM 16
17#define CONFIG_ETH_BUFSIZE 2048
18#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
19#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
20
21#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
22#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053023
24struct eth_mac_regs {
25 u32 conf; /* 0x00 */
26 u32 framefilt; /* 0x04 */
27 u32 hashtablehigh; /* 0x08 */
28 u32 hashtablelow; /* 0x0c */
29 u32 miiaddr; /* 0x10 */
30 u32 miidata; /* 0x14 */
31 u32 flowcontrol; /* 0x18 */
32 u32 vlantag; /* 0x1c */
33 u32 version; /* 0x20 */
34 u8 reserved_1[20];
35 u32 intreg; /* 0x38 */
36 u32 intmask; /* 0x3c */
37 u32 macaddr0hi; /* 0x40 */
38 u32 macaddr0lo; /* 0x44 */
39};
40
41/* MAC configuration register definitions */
42#define FRAMEBURSTENABLE (1 << 21)
43#define MII_PORTSELECT (1 << 15)
44#define FES_100 (1 << 14)
45#define DISABLERXOWN (1 << 13)
46#define FULLDPLXMODE (1 << 11)
47#define RXENABLE (1 << 2)
48#define TXENABLE (1 << 3)
49
50/* MII address register definitions */
51#define MII_BUSY (1 << 0)
52#define MII_WRITE (1 << 1)
53#define MII_CLKRANGE_60_100M (0)
54#define MII_CLKRANGE_100_150M (0x4)
55#define MII_CLKRANGE_20_35M (0x8)
56#define MII_CLKRANGE_35_60M (0xC)
57#define MII_CLKRANGE_150_250M (0x10)
58#define MII_CLKRANGE_250_300M (0x14)
59
60#define MIIADDRSHIFT (11)
61#define MIIREGSHIFT (6)
62#define MII_REGMSK (0x1F << 6)
63#define MII_ADDRMSK (0x1F << 11)
64
65
66struct eth_dma_regs {
67 u32 busmode; /* 0x00 */
68 u32 txpolldemand; /* 0x04 */
69 u32 rxpolldemand; /* 0x08 */
70 u32 rxdesclistaddr; /* 0x0c */
71 u32 txdesclistaddr; /* 0x10 */
72 u32 status; /* 0x14 */
73 u32 opmode; /* 0x18 */
74 u32 intenable; /* 0x1c */
Sonic Zhang2ddaf132015-01-29 13:37:31 +080075 u32 reserved1[2];
76 u32 axibus; /* 0x28 */
77 u32 reserved2[7];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053078 u32 currhosttxdesc; /* 0x48 */
79 u32 currhostrxdesc; /* 0x4c */
80 u32 currhosttxbuffaddr; /* 0x50 */
81 u32 currhostrxbuffaddr; /* 0x54 */
82};
83
84#define DW_DMA_BASE_OFFSET (0x1000)
85
Ian Campbell49692c52014-05-08 22:26:35 +010086/* Default DMA Burst length */
87#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
88#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
89#endif
90
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053091/* Bus mode register definitions */
92#define FIXEDBURST (1 << 16)
93#define PRIORXTX_41 (3 << 14)
94#define PRIORXTX_31 (2 << 14)
95#define PRIORXTX_21 (1 << 14)
96#define PRIORXTX_11 (0 << 14)
Ian Campbell49692c52014-05-08 22:26:35 +010097#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053098#define RXHIGHPRIO (1 << 1)
99#define DMAMAC_SRST (1 << 0)
100
101/* Poll demand definitions */
102#define POLL_DATA (0xFFFFFFFF)
103
104/* Operation mode definitions */
105#define STOREFORWARD (1 << 21)
106#define FLUSHTXFIFO (1 << 20)
107#define TXSTART (1 << 13)
108#define TXSECONDFRAME (1 << 2)
109#define RXSTART (1 << 1)
110
111/* Descriptior related definitions */
Vipin KUMAR97a6caa2012-03-26 00:09:53 +0000112#define MAC_MAX_FRAME_SZ (1600)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530113
114struct dmamacdescr {
115 u32 txrx_status;
116 u32 dmamac_cntl;
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200117 u32 dmamac_addr;
118 u32 dmamac_next;
Alexey Brodkina7b26db2014-03-21 16:16:57 +0400119} __aligned(ARCH_DMA_MINALIGN);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530120
121/*
122 * txrx_status definitions
123 */
124
125/* tx status bits definitions */
126#if defined(CONFIG_DW_ALTDESCRIPTOR)
127
128#define DESC_TXSTS_OWNBYDMA (1 << 31)
129#define DESC_TXSTS_TXINT (1 << 30)
130#define DESC_TXSTS_TXLAST (1 << 29)
131#define DESC_TXSTS_TXFIRST (1 << 28)
132#define DESC_TXSTS_TXCRCDIS (1 << 27)
133
134#define DESC_TXSTS_TXPADDIS (1 << 26)
135#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
136#define DESC_TXSTS_TXRINGEND (1 << 21)
137#define DESC_TXSTS_TXCHAIN (1 << 20)
138#define DESC_TXSTS_MSK (0x1FFFF << 0)
139
140#else
141
142#define DESC_TXSTS_OWNBYDMA (1 << 31)
143#define DESC_TXSTS_MSK (0x1FFFF << 0)
144
145#endif
146
147/* rx status bits definitions */
148#define DESC_RXSTS_OWNBYDMA (1 << 31)
149#define DESC_RXSTS_DAFILTERFAIL (1 << 30)
150#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
151#define DESC_RXSTS_FRMLENSHFT (16)
152
153#define DESC_RXSTS_ERROR (1 << 15)
154#define DESC_RXSTS_RXTRUNCATED (1 << 14)
155#define DESC_RXSTS_SAFILTERFAIL (1 << 13)
156#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
157#define DESC_RXSTS_RXDAMAGED (1 << 11)
158#define DESC_RXSTS_RXVLANTAG (1 << 10)
159#define DESC_RXSTS_RXFIRST (1 << 9)
160#define DESC_RXSTS_RXLAST (1 << 8)
161#define DESC_RXSTS_RXIPC_GIANT (1 << 7)
162#define DESC_RXSTS_RXCOLLISION (1 << 6)
163#define DESC_RXSTS_RXFRAMEETHER (1 << 5)
164#define DESC_RXSTS_RXWATCHDOG (1 << 4)
165#define DESC_RXSTS_RXMIIERROR (1 << 3)
166#define DESC_RXSTS_RXDRIBBLING (1 << 2)
167#define DESC_RXSTS_RXCRC (1 << 1)
168
169/*
170 * dmamac_cntl definitions
171 */
172
173/* tx control bits definitions */
174#if defined(CONFIG_DW_ALTDESCRIPTOR)
175
176#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
177#define DESC_TXCTRL_SIZE1SHFT (0)
178#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
179#define DESC_TXCTRL_SIZE2SHFT (16)
180
181#else
182
183#define DESC_TXCTRL_TXINT (1 << 31)
184#define DESC_TXCTRL_TXLAST (1 << 30)
185#define DESC_TXCTRL_TXFIRST (1 << 29)
186#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
187#define DESC_TXCTRL_TXCRCDIS (1 << 26)
188#define DESC_TXCTRL_TXRINGEND (1 << 25)
189#define DESC_TXCTRL_TXCHAIN (1 << 24)
190
191#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
192#define DESC_TXCTRL_SIZE1SHFT (0)
193#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
194#define DESC_TXCTRL_SIZE2SHFT (11)
195
196#endif
197
198/* rx control bits definitions */
199#if defined(CONFIG_DW_ALTDESCRIPTOR)
200
201#define DESC_RXCTRL_RXINTDIS (1 << 31)
202#define DESC_RXCTRL_RXRINGEND (1 << 15)
203#define DESC_RXCTRL_RXCHAIN (1 << 14)
204
205#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
206#define DESC_RXCTRL_SIZE1SHFT (0)
207#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
208#define DESC_RXCTRL_SIZE2SHFT (16)
209
210#else
211
212#define DESC_RXCTRL_RXINTDIS (1 << 31)
213#define DESC_RXCTRL_RXRINGEND (1 << 25)
214#define DESC_RXCTRL_RXCHAIN (1 << 24)
215
216#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
217#define DESC_RXCTRL_SIZE1SHFT (0)
218#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
219#define DESC_RXCTRL_SIZE2SHFT (11)
220
221#endif
222
223struct dw_eth_dev {
Ian Campbell18570752014-05-14 19:30:29 +0100224 struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
225 struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
226 char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
227 char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
228
Vipin Kumar9afc1af2012-05-07 13:06:44 +0530229 u32 interface;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300230 u32 max_speed;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530231 u32 tx_currdescnum;
232 u32 rx_currdescnum;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530233
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530234 struct eth_mac_regs *mac_regs_p;
235 struct eth_dma_regs *dma_regs_p;
Simon Glass75577ba2015-04-05 16:07:41 -0600236#ifndef CONFIG_DM_ETH
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530237 struct eth_device *dev;
Simon Glass75577ba2015-04-05 16:07:41 -0600238#endif
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300239#ifdef CONFIG_DM_GPIO
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100240 struct gpio_desc reset_gpio;
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300241#endif
242
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400243 struct phy_device *phydev;
244 struct mii_dev *bus;
Alexey Brodkined102be2013-09-25 19:27:48 +0400245};
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530246
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100247#ifdef CONFIG_DM_ETH
Sjoerd Simonsb9e08d02017-01-11 11:46:07 +0100248int designware_eth_ofdata_to_platdata(struct udevice *dev);
249int designware_eth_probe(struct udevice *dev);
250extern const struct eth_ops designware_eth_ops;
251
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100252struct dw_eth_pdata {
253 struct eth_pdata eth_pdata;
254 u32 reset_delays[3];
255};
Simon Glasse72ced22017-01-11 11:46:10 +0100256
257int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
258int designware_eth_enable(struct dw_eth_dev *priv);
259int designware_eth_send(struct udevice *dev, void *packet, int length);
260int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
261int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
262 int length);
263void designware_eth_stop(struct udevice *dev);
264int designware_eth_write_hwaddr(struct udevice *dev);
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100265#endif
266
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530267#endif