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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2000
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * (C) Copyright 2004
6 * ARM Ltd.
7 * Philippe Robin, <philippe.robin@arm.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Andreas Engel48d01922008-09-08 14:30:53 +020028/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
wdenk3d3befa2004-03-14 15:06:13 +000029
30#include <common.h>
Stuart Wood8b616ed2008-06-02 16:42:19 -040031#include <watchdog.h>
Matt Waddel249d5212010-10-07 15:48:46 -060032#include <asm/io.h>
Andreas Engel20c92262008-09-08 10:17:31 +020033#include "serial_pl01x.h"
wdenk3d3befa2004-03-14 15:06:13 +000034
Andreas Engel20c92262008-09-08 10:17:31 +020035/*
36 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
37 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
38 * Versatile PB has four UARTs.
39 */
wdenk3d3befa2004-03-14 15:06:13 +000040#define CONSOLE_PORT CONFIG_CONS_INDEX
wdenk6705d812004-08-02 23:22:59 +000041static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
42#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
wdenk3d3befa2004-03-14 15:06:13 +000043
Andreas Engel20c92262008-09-08 10:17:31 +020044static void pl01x_putc (int portnum, char c);
45static int pl01x_getc (int portnum);
46static int pl01x_tstc (int portnum);
Matt Waddel249d5212010-10-07 15:48:46 -060047unsigned int baudrate = CONFIG_BAUDRATE;
48DECLARE_GLOBAL_DATA_PTR;
wdenk3d3befa2004-03-14 15:06:13 +000049
Rabin Vincent72d5e442010-05-05 09:23:07 +053050static struct pl01x_regs *pl01x_get_regs(int portnum)
51{
52 return (struct pl01x_regs *) port[portnum];
53}
54
Andreas Engel48d01922008-09-08 14:30:53 +020055#ifdef CONFIG_PL010_SERIAL
wdenk3d3befa2004-03-14 15:06:13 +000056
57int serial_init (void)
58{
Rabin Vincent72d5e442010-05-05 09:23:07 +053059 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
wdenk42dfe7a2004-03-14 22:25:36 +000060 unsigned int divisor;
wdenk3d3befa2004-03-14 15:06:13 +000061
Matt Waddel249d5212010-10-07 15:48:46 -060062 /* First, disable everything */
Rabin Vincent72d5e442010-05-05 09:23:07 +053063 writel(0, &regs->pl010_cr);
wdenk3d3befa2004-03-14 15:06:13 +000064
Matt Waddel249d5212010-10-07 15:48:46 -060065 /* Set baud rate */
66 switch (baudrate) {
wdenk42dfe7a2004-03-14 22:25:36 +000067 case 9600:
68 divisor = UART_PL010_BAUD_9600;
69 break;
wdenk3d3befa2004-03-14 15:06:13 +000070
wdenk42dfe7a2004-03-14 22:25:36 +000071 case 19200:
72 divisor = UART_PL010_BAUD_9600;
73 break;
wdenk3d3befa2004-03-14 15:06:13 +000074
wdenk42dfe7a2004-03-14 22:25:36 +000075 case 38400:
76 divisor = UART_PL010_BAUD_38400;
77 break;
wdenk3d3befa2004-03-14 15:06:13 +000078
wdenk42dfe7a2004-03-14 22:25:36 +000079 case 57600:
80 divisor = UART_PL010_BAUD_57600;
81 break;
wdenk3d3befa2004-03-14 15:06:13 +000082
wdenk42dfe7a2004-03-14 22:25:36 +000083 case 115200:
84 divisor = UART_PL010_BAUD_115200;
85 break;
wdenk3d3befa2004-03-14 15:06:13 +000086
wdenk42dfe7a2004-03-14 22:25:36 +000087 default:
88 divisor = UART_PL010_BAUD_38400;
89 }
wdenk3d3befa2004-03-14 15:06:13 +000090
Rabin Vincent72d5e442010-05-05 09:23:07 +053091 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
92 writel(divisor & 0xff, &regs->pl010_lcrl);
wdenk3d3befa2004-03-14 15:06:13 +000093
Matt Waddel249d5212010-10-07 15:48:46 -060094 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
Rabin Vincent72d5e442010-05-05 09:23:07 +053095 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, &regs->pl010_lcrh);
wdenk3d3befa2004-03-14 15:06:13 +000096
Matt Waddel249d5212010-10-07 15:48:46 -060097 /* Finally, enable the UART */
Rabin Vincent72d5e442010-05-05 09:23:07 +053098 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
wdenk42dfe7a2004-03-14 22:25:36 +000099
Andreas Engel20c92262008-09-08 10:17:31 +0200100 return 0;
wdenk3d3befa2004-03-14 15:06:13 +0000101}
102
Andreas Engel48d01922008-09-08 14:30:53 +0200103#endif /* CONFIG_PL010_SERIAL */
Andreas Engel20c92262008-09-08 10:17:31 +0200104
Andreas Engel48d01922008-09-08 14:30:53 +0200105#ifdef CONFIG_PL011_SERIAL
Andreas Engel20c92262008-09-08 10:17:31 +0200106
107int serial_init (void)
108{
Rabin Vincent72d5e442010-05-05 09:23:07 +0530109 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
Andreas Engel20c92262008-09-08 10:17:31 +0200110 unsigned int temp;
111 unsigned int divider;
112 unsigned int remainder;
113 unsigned int fraction;
John Rigby910f1ae2011-04-19 10:42:39 +0000114 unsigned int lcr;
115
116#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
117 /* Empty RX fifo if necessary */
118 if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
119 while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
120 readl(&regs->dr);
121 }
122#endif
Andreas Engel20c92262008-09-08 10:17:31 +0200123
Matt Waddel249d5212010-10-07 15:48:46 -0600124 /* First, disable everything */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530125 writel(0, &regs->pl011_cr);
Andreas Engel20c92262008-09-08 10:17:31 +0200126
127 /*
Matt Waddel249d5212010-10-07 15:48:46 -0600128 * Set baud rate
129 *
130 * IBRD = UART_CLK / (16 * BAUD_RATE)
131 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
Andreas Engel20c92262008-09-08 10:17:31 +0200132 */
Matt Waddel249d5212010-10-07 15:48:46 -0600133 temp = 16 * baudrate;
Andreas Engel20c92262008-09-08 10:17:31 +0200134 divider = CONFIG_PL011_CLOCK / temp;
135 remainder = CONFIG_PL011_CLOCK % temp;
Matt Waddel249d5212010-10-07 15:48:46 -0600136 temp = (8 * remainder) / baudrate;
Andreas Engel20c92262008-09-08 10:17:31 +0200137 fraction = (temp >> 1) + (temp & 1);
138
Rabin Vincent72d5e442010-05-05 09:23:07 +0530139 writel(divider, &regs->pl011_ibrd);
140 writel(fraction, &regs->pl011_fbrd);
Andreas Engel20c92262008-09-08 10:17:31 +0200141
Matt Waddel249d5212010-10-07 15:48:46 -0600142 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
John Rigby910f1ae2011-04-19 10:42:39 +0000143 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
144 writel(lcr, &regs->pl011_lcrh);
Andreas Engel20c92262008-09-08 10:17:31 +0200145
John Rigby910f1ae2011-04-19 10:42:39 +0000146#ifdef CONFIG_PL011_SERIAL_RLCR
147 {
148 int i;
149
150 /*
151 * Program receive line control register after waiting
152 * 10 bus cycles. Delay be writing to readonly register
153 * 10 times
154 */
155 for (i = 0; i < 10; i++)
156 writel(lcr, &regs->fr);
157
158 writel(lcr, &regs->pl011_rlcr);
159 }
160#endif
Matt Waddel249d5212010-10-07 15:48:46 -0600161 /* Finally, enable the UART */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530162 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
163 &regs->pl011_cr);
Andreas Engel20c92262008-09-08 10:17:31 +0200164
165 return 0;
166}
167
Andreas Engel48d01922008-09-08 14:30:53 +0200168#endif /* CONFIG_PL011_SERIAL */
Andreas Engel20c92262008-09-08 10:17:31 +0200169
wdenk42dfe7a2004-03-14 22:25:36 +0000170void serial_putc (const char c)
wdenk3d3befa2004-03-14 15:06:13 +0000171{
172 if (c == '\n')
Andreas Engel20c92262008-09-08 10:17:31 +0200173 pl01x_putc (CONSOLE_PORT, '\r');
wdenk3d3befa2004-03-14 15:06:13 +0000174
Andreas Engel20c92262008-09-08 10:17:31 +0200175 pl01x_putc (CONSOLE_PORT, c);
wdenk3d3befa2004-03-14 15:06:13 +0000176}
177
wdenk42dfe7a2004-03-14 22:25:36 +0000178void serial_puts (const char *s)
wdenk3d3befa2004-03-14 15:06:13 +0000179{
180 while (*s) {
181 serial_putc (*s++);
182 }
183}
184
wdenk42dfe7a2004-03-14 22:25:36 +0000185int serial_getc (void)
wdenk3d3befa2004-03-14 15:06:13 +0000186{
Andreas Engel20c92262008-09-08 10:17:31 +0200187 return pl01x_getc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000188}
189
wdenk42dfe7a2004-03-14 22:25:36 +0000190int serial_tstc (void)
wdenk3d3befa2004-03-14 15:06:13 +0000191{
Andreas Engel20c92262008-09-08 10:17:31 +0200192 return pl01x_tstc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000193}
194
wdenk42dfe7a2004-03-14 22:25:36 +0000195void serial_setbrg (void)
wdenk3d3befa2004-03-14 15:06:13 +0000196{
Linus Walleij96baa4c2011-10-02 11:52:52 +0000197 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
198
Matt Waddel249d5212010-10-07 15:48:46 -0600199 baudrate = gd->baudrate;
Linus Walleij96baa4c2011-10-02 11:52:52 +0000200 /*
201 * Flush FIFO and wait for non-busy before changing baudrate to avoid
202 * crap in console
203 */
204 while (!(readl(&regs->fr) & UART_PL01x_FR_TXFE))
205 WATCHDOG_RESET();
206 while (readl(&regs->fr) & UART_PL01x_FR_BUSY)
207 WATCHDOG_RESET();
Matt Waddel249d5212010-10-07 15:48:46 -0600208 serial_init();
wdenk3d3befa2004-03-14 15:06:13 +0000209}
210
Andreas Engel20c92262008-09-08 10:17:31 +0200211static void pl01x_putc (int portnum, char c)
wdenk3d3befa2004-03-14 15:06:13 +0000212{
Rabin Vincent72d5e442010-05-05 09:23:07 +0530213 struct pl01x_regs *regs = pl01x_get_regs(portnum);
214
wdenk42dfe7a2004-03-14 22:25:36 +0000215 /* Wait until there is space in the FIFO */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530216 while (readl(&regs->fr) & UART_PL01x_FR_TXFF)
Stuart Wood8b616ed2008-06-02 16:42:19 -0400217 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000218
219 /* Send the character */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530220 writel(c, &regs->dr);
wdenk3d3befa2004-03-14 15:06:13 +0000221}
222
Andreas Engel20c92262008-09-08 10:17:31 +0200223static int pl01x_getc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000224{
Rabin Vincent72d5e442010-05-05 09:23:07 +0530225 struct pl01x_regs *regs = pl01x_get_regs(portnum);
wdenk42dfe7a2004-03-14 22:25:36 +0000226 unsigned int data;
wdenk3d3befa2004-03-14 15:06:13 +0000227
wdenk42dfe7a2004-03-14 22:25:36 +0000228 /* Wait until there is data in the FIFO */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530229 while (readl(&regs->fr) & UART_PL01x_FR_RXFE)
Stuart Wood8b616ed2008-06-02 16:42:19 -0400230 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000231
Rabin Vincent72d5e442010-05-05 09:23:07 +0530232 data = readl(&regs->dr);
wdenk42dfe7a2004-03-14 22:25:36 +0000233
234 /* Check for an error flag */
235 if (data & 0xFFFFFF00) {
236 /* Clear the error */
Rabin Vincent72d5e442010-05-05 09:23:07 +0530237 writel(0xFFFFFFFF, &regs->ecr);
wdenk42dfe7a2004-03-14 22:25:36 +0000238 return -1;
239 }
240
241 return (int) data;
wdenk3d3befa2004-03-14 15:06:13 +0000242}
243
Andreas Engel20c92262008-09-08 10:17:31 +0200244static int pl01x_tstc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000245{
Rabin Vincent72d5e442010-05-05 09:23:07 +0530246 struct pl01x_regs *regs = pl01x_get_regs(portnum);
247
Stuart Wood8b616ed2008-06-02 16:42:19 -0400248 WATCHDOG_RESET();
Rabin Vincent72d5e442010-05-05 09:23:07 +0530249 return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
wdenk3d3befa2004-03-14 15:06:13 +0000250}