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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liewdd9f0542010-03-11 22:12:53 -06002/*
3 * ColdFire cache
4 *
Alison Wang45370e12012-10-18 19:25:51 +00005 * Copyright 2004-2012 Freescale Semiconductor, Inc.
TsiChung Liewdd9f0542010-03-11 22:12:53 -06006 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewdd9f0542010-03-11 22:12:53 -06007 */
8
9#ifndef __CACHE_H
10#define __CACHE_H
11
12#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
13 defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
14#define CONFIG_CF_V2
15#endif
16
angelo@sysam.ite77e65d2015-02-12 01:40:00 +010017#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
18 defined(CONFIG_MCF5301x)
TsiChung Liewdd9f0542010-03-11 22:12:53 -060019#define CONFIG_CF_V3
20#endif
21
22#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
23#define CONFIG_CF_V4
Alison Wang45370e12012-10-18 19:25:51 +000024#elif defined(CONFIG_MCF5441x)
TsiChung Liewdd9f0542010-03-11 22:12:53 -060025#define CONFIG_CF_V4E /* Four Extra ACRn */
26#endif
TsiChung Liewdd9f0542010-03-11 22:12:53 -060027
28/* ***** CACR ***** */
29/* V2 Core */
30#ifdef CONFIG_CF_V2
31
32#define CF_CACR_CENB (1 << 31)
33#define CF_CACR_CPD (1 << 28)
34#define CF_CACR_CFRZ (1 << 27)
35#define CF_CACR_CEIB (1 << 10)
36#define CF_CACR_DCM (1 << 9)
37#define CF_CACR_DBWE (1 << 8)
38
39#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
40#define CF_CACR_DWP (1 << 6)
41#else
42#define CF_CACR_CINV (1 << 24)
43#define CF_CACR_DISI (1 << 23)
44#define CF_CACR_DISD (1 << 22)
45#define CF_CACR_INVI (1 << 21)
46#define CF_CACR_INVD (1 << 20)
47#define CF_CACR_DWP (1 << 5)
48#define CF_CACR_EUSP (1 << 4)
49#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */
50
51#endif /* CONFIG_CF_V2 */
52
53/* V3 Core */
54#ifdef CONFIG_CF_V3
55
56#define CF_CACR_EC (1 << 31)
57#define CF_CACR_ESB (1 << 29)
58#define CF_CACR_DPI (1 << 28)
59#define CF_CACR_HLCK (1 << 27)
60#define CF_CACR_CINVA (1 << 24)
61#define CF_CACR_DNFB (1 << 10)
62#define CF_CACR_DCM_UNMASK 0xFFFFFCFF
63#define CF_CACR_DCM_WT (0 << 8)
64#define CF_CACR_DCM_CB (1 << 8)
65#define CF_CACR_DCM_P (2 << 8)
66#define CF_CACR_DCM_IP (3 << 8)
67#define CF_CACR_DW (1 << 5)
68#define CF_CACR_EUSP (1 << 4)
69
70#endif /* CONFIG_CF_V3 */
71
72/* V4 Core */
Alison Wang45370e12012-10-18 19:25:51 +000073#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
TsiChung Liewdd9f0542010-03-11 22:12:53 -060074
75#define CF_CACR_DEC (1 << 31)
76#define CF_CACR_DW (1 << 30)
77#define CF_CACR_DESB (1 << 29)
78#define CF_CACR_DDPI (1 << 28)
79#define CF_CACR_DHLCK (1 << 27)
80#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF)
81#define CF_CACR_DDCM_WT (0 << 25)
82#define CF_CACR_DDCM_CB (1 << 25)
83#define CF_CACR_DDCM_P (2 << 25)
84#define CF_CACR_DDCM_IP (3 << 25)
85#define CF_CACR_DCINVA (1 << 24)
86
87#define CF_CACR_DDSP (1 << 23)
88#define CF_CACR_BEC (1 << 19)
89#define CF_CACR_BCINVA (1 << 18)
90#define CF_CACR_IEC (1 << 15)
91#define CF_CACR_DNFB (1 << 13)
92#define CF_CACR_IDPI (1 << 12)
93#define CF_CACR_IHLCK (1 << 11)
94#define CF_CACR_IDCM (1 << 10)
95#define CF_CACR_ICINVA (1 << 8)
96#define CF_CACR_IDSP (1 << 7)
97#define CF_CACR_EUSP (1 << 5)
98
Alison Wang45370e12012-10-18 19:25:51 +000099#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600100#define CF_CACR_IVO (1 << 20)
101#define CF_CACR_SPA (1 << 14)
102#else
103#define CF_CACR_DF (1 << 4)
104#endif
105
106#endif /* CONFIG_CF_V4 */
107
108/* ***** ACR ***** */
109#define CF_ACR_ADR_UNMASK (0x00FFFFFF)
110#define CF_ACR_ADR(x) ((x & 0xFF) << 24)
111#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF)
112#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16)
113#define CF_ACR_EN (1 << 15)
114#define CF_ACR_SM_UNMASK (0xFFFF9FFF)
115#define CF_ACR_SM_UM (0 << 13)
116#define CF_ACR_SM_SM (1 << 13)
117#define CF_ACR_SM_ALL (3 << 13)
118#define CF_ACR_WP (1 << 2)
119
120/* V2 Core */
121#ifdef CONFIG_CF_V2
122#define CF_ACR_CM (1 << 6)
123#define CF_ACR_BWE (1 << 5)
124#else
125/* V3 & V4 */
126#define CF_ACR_CM_UNMASK (0xFFFFFF9F)
127#define CF_ACR_CM_WT (0 << 5)
128#define CF_ACR_CM_CB (1 << 5)
129#define CF_ACR_CM_P (2 << 5)
130#define CF_ACR_CM_IP (3 << 5)
131#endif /* CONFIG_CF_V2 */
132
133/* V4 Core */
Alison Wang45370e12012-10-18 19:25:51 +0000134#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600135#define CF_ACR_AMM (1 << 10)
136#define CF_ACR_SP (1 << 3)
137#endif /* CONFIG_CF_V4 */
138
139
140#ifndef CONFIG_SYS_CACHE_ICACR
141#define CONFIG_SYS_CACHE_ICACR 0
142#endif
143
144#ifndef CONFIG_SYS_CACHE_DCACR
145#ifdef CONFIG_SYS_CACHE_ICACR
146#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR
147#else
148#define CONFIG_SYS_CACHE_DCACR 0
149#endif
150#endif
151
152#ifndef CONFIG_SYS_CACHE_ACR0
153#define CONFIG_SYS_CACHE_ACR0 0
154#endif
155
156#ifndef CONFIG_SYS_CACHE_ACR1
157#define CONFIG_SYS_CACHE_ACR1 0
158#endif
159
160#ifndef CONFIG_SYS_CACHE_ACR2
161#define CONFIG_SYS_CACHE_ACR2 0
162#endif
163
164#ifndef CONFIG_SYS_CACHE_ACR3
165#define CONFIG_SYS_CACHE_ACR3 0
166#endif
167
168#ifndef CONFIG_SYS_CACHE_ACR4
169#define CONFIG_SYS_CACHE_ACR4 0
170#endif
171
172#ifndef CONFIG_SYS_CACHE_ACR5
173#define CONFIG_SYS_CACHE_ACR5 0
174#endif
175
176#ifndef CONFIG_SYS_CACHE_ACR6
177#define CONFIG_SYS_CACHE_ACR6 0
178#endif
179
180#ifndef CONFIG_SYS_CACHE_ACR7
181#define CONFIG_SYS_CACHE_ACR7 0
182#endif
183
184#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
185
186#ifndef __ASSEMBLY__ /* put C only stuff in this section */
187
188void icache_invalid(void);
189void dcache_invalid(void);
190
191#endif
192
Anton Staafa8fc12e2011-10-17 16:46:04 -0700193/*
194 * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer
195 * alignment unless the board configuration has specified a new value.
196 */
197#ifdef CONFIG_SYS_CACHELINE_SIZE
198#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
199#else
200#define ARCH_DMA_MINALIGN 16
201#endif
202
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600203#endif /* __CACHE_H */