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wdenk0f8c9762002-08-19 11:57:05 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk0f8c9762002-08-19 11:57:05 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37#define CONFIG_C2MON 1 /* ...on a C2MON module */
38
39#define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */
40
41#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
44#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
45#if 0
46#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47#else
48#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49#endif
50
51#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
54
55#undef CONFIG_BOOTARGS
56#define CONFIG_BOOTCOMMAND \
57 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010058 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
59 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk0f8c9762002-08-19 11:57:05 +000060 "bootm"
61
62#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
63#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
64
65#undef CONFIG_WATCHDOG /* watchdog disabled */
66
67#undef CONFIG_STATUS_LED /* Status LED disabled */
68
69#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
70
71#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
72
73#define CONFIG_MAC_PARTITION
74#define CONFIG_DOS_PARTITION
75
76#define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */
77
78#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
79
80#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk414eec32005-04-02 22:37:54 +000081 CFG_CMD_DATE | \
wdenk0f8c9762002-08-19 11:57:05 +000082 CFG_CMD_DHCP | \
83 CFG_CMD_IDE | \
wdenk414eec32005-04-02 22:37:54 +000084 CFG_CMD_NFS | \
85 CFG_CMD_SNTP )
wdenk0f8c9762002-08-19 11:57:05 +000086
87/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
88#include <cmd_confdefs.h>
89
90/*
91 * Miscellaneous configurable options
92 */
93#define CFG_LONGHELP /* undef to save memory */
94#define CFG_PROMPT "=> " /* Monitor Command Prompt */
95
96#undef CFG_HUSH_PARSER /* use "hush" command parser */
97#ifdef CFG_HUSH_PARSER
98#define CFG_PROMPT_HUSH_PS2 "> "
99#endif
100
101#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
102#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
103#else
104#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
105#endif
106#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
107#define CFG_MAXARGS 16 /* max number of command args */
108#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
109
110#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
111#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
112
113#define CFG_LOAD_ADDR 0x100000 /* default load address */
114
115#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
116
117#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
118
119/*
120 * Low Level Configuration Settings
121 * (address mappings, register initial values, etc.)
122 * You should know what you are doing if you make changes here.
123 */
124/*-----------------------------------------------------------------------
125 * Internal Memory Mapped Register
126 */
127#define CFG_IMMR 0xFFF00000
128
129/*-----------------------------------------------------------------------
130 * Definitions for initial stack pointer and data area (in DPRAM)
131 */
132#define CFG_INIT_RAM_ADDR CFG_IMMR
133#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
134#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
135#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
136#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
137
138/*-----------------------------------------------------------------------
139 * Start addresses for the final memory configuration
140 * (Set up by the startup code)
141 * Please note that CFG_SDRAM_BASE _must_ start at 0
142 */
143#define CFG_SDRAM_BASE 0x00000000
144#define CFG_FLASH_BASE 0x40000000
145#if defined(DEBUG)
146#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
147#else
148#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
149#endif
150#define CFG_MONITOR_BASE CFG_FLASH_BASE
151#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
152
153/*
154 * For booting Linux, the board info and command line data
155 * have to be in the first 8 MB of memory, since this is
156 * the maximum mapped by the Linux kernel during initialization.
157 */
158#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
159
160/*-----------------------------------------------------------------------
161 * FLASH organization
162 */
163#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
164#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
165
166#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
167#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
168
169#define CFG_ENV_IS_IN_FLASH 1
170#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
171#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
172
173/*-----------------------------------------------------------------------
174 * Cache Configuration
175 */
176#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
177#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
178#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
179#endif
180
181/*-----------------------------------------------------------------------
182 * SYPCR - System Protection Control 11-9
183 * SYPCR can only be written once after reset!
184 *-----------------------------------------------------------------------
185 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
186 */
187#if defined(CONFIG_WATCHDOG)
188#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
189 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
190#else
191#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
192#endif
193
194/*-----------------------------------------------------------------------
195 * SIUMCR - SIU Module Configuration 11-6
196 *-----------------------------------------------------------------------
197 * PCMCIA config., multi-function pin tri-state
198 */
199#ifndef CONFIG_CAN_DRIVER
200#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
201#else /* we must activate GPL5 in the SIUMCR for CAN */
202#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
203#endif /* CONFIG_CAN_DRIVER */
204
205/*-----------------------------------------------------------------------
206 * TBSCR - Time Base Status and Control 11-26
207 *-----------------------------------------------------------------------
208 * Clear Reference Interrupt Status, Timebase freezing enabled
209 */
210#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
211
212/*-----------------------------------------------------------------------
213 * RTCSC - Real-Time Clock Status and Control Register 11-27
214 *-----------------------------------------------------------------------
215 */
216#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
217
218/*-----------------------------------------------------------------------
219 * PISCR - Periodic Interrupt Status and Control 11-31
220 *-----------------------------------------------------------------------
221 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
222 */
223#define CFG_PISCR (PISCR_PS | PISCR_PITF)
224
225/*-----------------------------------------------------------------------
226 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
227 *-----------------------------------------------------------------------
228 * Reset PLL lock status sticky bit, timer expired status bit and timer
229 * interrupt status bit
230 *
231 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
232 */
233#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
234#define CFG_PLPRCR \
235 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
236#else /* up to 50 MHz we use a 1:1 clock */
237#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
238#endif /* CONFIG_80MHz */
239
240/*-----------------------------------------------------------------------
241 * SCCR - System Clock and reset Control Register 15-27
242 *-----------------------------------------------------------------------
243 * Set clock output, timebase and RTC source and divider,
244 * power management and some other internal clocks
245 */
246#define SCCR_MASK SCCR_EBDF11
247#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
248#define CFG_SCCR (/* SCCR_TBS | */ \
249 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
250 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
251 SCCR_DFALCD00)
252#else /* up to 50 MHz we use a 1:1 clock */
253#define CFG_SCCR (SCCR_TBS | \
254 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
255 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
256 SCCR_DFALCD00)
257#endif /* CONFIG_80MHz */
258
259/*-----------------------------------------------------------------------
260 * PCMCIA stuff
261 *-----------------------------------------------------------------------
262 *
263 */
264#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
265#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
266#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
267#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
268#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
269#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
270#define CFG_PCMCIA_IO_ADDR (0xEC000000)
271#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
272
273/*-----------------------------------------------------------------------
274 * PCMCIA Power Switch
275 *
276 * The C2MON uses a TPS2211A PC-Card Power-Interface Switch to
277 * control the voltages on the PCMCIA slot which is connected
278 * to Port C (all outputs) and Port B (Over-Current Input)
279 *-----------------------------------------------------------------------
280 */
281 /* Output pins */
282#define TPS2211_VCCD0 0x0002 /* PC.14 */
283#define TPS2211_VCCD1 0x0004 /* PC.13 */
284#define TPS2211_VPPD0 0x0008 /* PC.12 */
285#define TPS2211_VPPD1 0x0010 /* PC.11 */
286#define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \
287 TPS2211_VPPD0 | TPS2211_VPPD1 )
288
289 /* Input pins */
290#define TPS2211_OC 0x00000200 /* PB.22: Over-Current */
291#define TPS2211_INPUTS ( TPS2211_OC )
292
293/*-----------------------------------------------------------------------
294 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
295 *-----------------------------------------------------------------------
296 */
297
298#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
299
300#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
301#undef CONFIG_IDE_LED /* LED for ide not supported */
302#undef CONFIG_IDE_RESET /* reset for ide not supported */
303
304#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
305#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
306
307#define CFG_ATA_IDE0_OFFSET 0x0000
308
309#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
310
311/* Offset for data I/O */
312#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
313
314/* Offset for normal register accesses */
315#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
316
317/* Offset for alternate registers */
318#define CFG_ATA_ALT_OFFSET 0x0100
319
320
321/*-----------------------------------------------------------------------
322 *
323 *-----------------------------------------------------------------------
324 *
325 */
wdenk0f8c9762002-08-19 11:57:05 +0000326#define CFG_DER 0
327
328/*
329 * Init Memory Controller:
330 *
331 * BR0/1 and OR0/1 (FLASH)
332 */
333
334#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
335#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
336
337/* used to re-map FLASH both when starting from SRAM or FLASH:
338 * restrict access enough to keep SRAM working (if any)
339 * but not too much to meddle with FLASH accesses
340 */
341#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
342#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
343
344/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
345#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
346 OR_SCY_5_CLK | OR_EHTR)
347
348#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
349#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
350#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
351
352#define CFG_OR1_REMAP CFG_OR0_REMAP
353#define CFG_OR1_PRELIM CFG_OR0_PRELIM
354#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
355
356/*
357 * BR2/3 and OR2/3 (SDRAM)
358 *
359 */
360#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
361#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
362#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
363
364/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
365#define CFG_OR_TIMING_SDRAM 0x00000A00
366
367#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
368#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
369
370#ifndef CONFIG_CAN_DRIVER
371#define CFG_OR3_PRELIM CFG_OR2_PRELIM
372#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
373#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
374#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
375#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
376#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
377#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
378 BR_PS_8 | BR_MS_UPMB | BR_V )
379#endif /* CONFIG_CAN_DRIVER */
380
381/*
382 * Memory Periodic Timer Prescaler
383 */
384
385/* periodic timer for refresh */
386#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
387
388/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
389#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
390#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
391
392/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
393#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
394#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
395
396/*
397 * MAMR settings for SDRAM
398 */
399
400/* 8 column SDRAM */
401#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
402 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
403 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
404/* 9 column SDRAM */
405#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
406 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
407 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
408
409
410/*
411 * Internal Definitions
412 *
413 * Boot Flags
414 */
415#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
416#define BOOTFLAG_WARM 0x02 /* Software reboot */
417
418#endif /* __CONFIG_H */