Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 5992f2579739c421cbdc1b6dd0054c636f376ba0 / . / arch / arm / dts / imx6ull-colibri.dtsi
blob: fca53119fe7914d0b7ad356a41afcb7f03816c6c [file] [log] [blame]
Igor Opaniuk7d6ca122019-10-16 13:39:35 +0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 Toradex AG
4 */
5
6/dts-v1/;
7#include <dt-bindings/gpio/gpio.h>
8#include "imx6ull.dtsi"
9
10/ {
11 aliases {
12 u-boot,dm-pre-reloc;
13 mmc0 = &usdhc1;
14 usb0 = &usbotg1; /* required for ums */
15 display0 = &lcdif;
16 };
17
18 chosen {
19 stdout-path = &uart1;
20 };
21
22 reg_module_3v3: regulator-module-3v3 {
23 compatible = "regulator-fixed";
24 regulator-always-on;
25 regulator-name = "+V3.3";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
28 };
29
30 reg_module_3v3_avdd: regulator-module-3v3-avdd {
31 compatible = "regulator-fixed";
32 regulator-always-on;
33 regulator-name = "+V3.3_AVDD_AUDIO";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 };
37
38 reg_5v0: regulator-5v0 {
39 compatible = "regulator-fixed";
40 regulator-name = "5V";
41 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <5000000>;
43 };
44
45 reg_sd1_vmmc: regulator-sd1-vmmc {
46 compatible = "regulator-gpio";
47 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
50 regulator-always-on;
51 regulator-name = "+V3.3_1.8_SD";
52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <3300000>;
54 states = <1800000 0x1 3300000 0x0>;
55 vin-supply = <&reg_module_3v3>;
56 };
57
58 reg_usbh_vbus: regulator-usbh-vbus {
59 compatible = "regulator-fixed";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_usbh_reg>;
62 regulator-name = "VCC_USB[1-4]";
63 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>;
65 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
66 vin-supply = <&reg_5v0>;
67 };
68};
69
70&adc1 {
71 num-channels = <10>;
72 vref-supply = <&reg_module_3v3_avdd>;
73};
74
75/* Colibri SPI */
76&ecspi1 {
77 cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
80};
81
82/* Ethernet */
83&fec2 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_enet2>;
86 phy-mode = "rmii";
87 phy-handle = <&ethphy1>;
88 status = "okay";
89
90 mdio {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 ethphy1: ethernet-phy@2 {
95 compatible = "ethernet-phy-ieee802.3-c22";
96 max-speed = <100>;
97 reg = <2>;
98 };
99 };
100};
101
102/* NAND */
103&gpmi {
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_gpmi_nand>;
106 nand-on-flash-bbt;
107 nand-ecc-mode = "hw";
108 nand-ecc-strength = <8>;
109 nand-ecc-step-size = <512>;
110 status = "okay";
111};
112
113/*
114 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
115 */
116&i2c1 {
117 pinctrl-names = "default", "gpio";
118 pinctrl-0 = <&pinctrl_i2c1>;
119 pinctrl-1 = <&pinctrl_i2c1_gpio>;
120 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
121 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
122 status = "okay";
123};
124
125/*
126 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
127 * touch screen controller
128 */
129&i2c2 {
130 pinctrl-names = "default", "gpio";
131 pinctrl-0 = <&pinctrl_i2c2>;
132 pinctrl-1 = <&pinctrl_i2c2_gpio>;
133 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
134 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
135 status = "okay";
136
137 ad7879@2c {
138 compatible = "adi,ad7879-1";
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
141 reg = <0x2c>;
142 interrupt-parent = <&gpio5>;
143 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
144 touchscreen-max-pressure = <4096>;
145 adi,resistance-plate-x = <120>;
146 adi,first-conversion-delay = /bits/ 8 <3>;
147 adi,acquisition-time = /bits/ 8 <1>;
148 adi,median-filter-size = /bits/ 8 <2>;
149 adi,averaging = /bits/ 8 <1>;
150 adi,conversion-interval = /bits/ 8 <255>;
151 };
152};
153
154&lcdif {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_lcdif_dat
157 &pinctrl_lcdif_ctrl>;
158 status = "okay";
159 display = <&display0>;
160 u-boot,dm-pre-reloc;
161
162 display0: display0 {
163 bits-per-pixel = <18>;
164 bus-width = <24>;
165 status = "okay";
166
167 display-timings {
168 native-mode = <&timing_vga>;
169 timing_vga: 640x480 {
170 u-boot,dm-pre-reloc;
171 clock-frequency = <25175000>;
172 hactive = <640>;
173 vactive = <480>;
174 hback-porch = <48>;
175 hfront-porch = <16>;
176 vback-porch = <33>;
177 vfront-porch = <10>;
178 hsync-len = <96>;
179 vsync-len = <2>;
180
181 de-active = <1>;
182 hsync-active = <0>;
183 vsync-active = <0>;
184 pixelclk-active = <0>;
185 };
186 };
187 };
188};
189
190/* PWM <A> */
191&pwm4 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_pwm4>;
194 #pwm-cells = <3>;
195};
196
197/* PWM <B> */
198&pwm5 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_pwm5>;
201 #pwm-cells = <3>;
202};
203
204/* PWM <C> */
205&pwm6 {
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_pwm6>;
208 #pwm-cells = <3>;
209};
210
211/* PWM <D> */
212&pwm7 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_pwm7>;
215 #pwm-cells = <3>;
216};
217
218&sdma {
219 status = "okay";
220};
221
222&snvs_pwrkey {
223 status = "disabled";
224};
225
226/* Colibri UART_A */
227&uart1 {
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
230 uart-has-rtscts;
231 fsl,dte-mode;
232 status = "okay";
233};
234
235/* Colibri UART_B */
236&uart2 {
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_uart2>;
239 uart-has-rtscts;
240 fsl,dte-mode;
241};
242
243/* Colibri UART_C */
244&uart5 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_uart5>;
247 fsl,dte-mode;
248};
249
250/* Colibri USBC */
251&usbotg1 {
252 dr_mode = "host";
253 srp-disable;
254 hnp-disable;
255 adp-disable;
256 status = "okay";
257};
258
259/* Colibri USBH */
260&usbotg2 {
261 dr_mode = "host";
262 vbus-supply = <&reg_usbh_vbus>;
263 status = "okay";
264};
265
266/* Colibri MMC */
267&usdhc1 {
268 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
269 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
270 assigned-clock-rates = <0>, <198000000>;
271 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
272 pinctrl-names = "default", "state_100mhz", "state_200mhz";
273 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
274 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
275 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
276 vmmc-supply = <&reg_sd1_vmmc>;
277 status = "okay";
278};
279
280&iomuxc {
281 pinctrl_can_int: canint-grp {
282 fsl,pins = <
283 /* SODIMM 73 */
284 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14
285 >;
286 };
287
288 pinctrl_enet2: enet2-grp {
289 fsl,pins = <
290 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
291 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
292 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
293 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
294 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
295 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
296 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
297 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
298 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
299 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
300 >;
301 };
302
303 pinctrl_ecspi1_cs: ecspi1-cs-grp {
304 fsl,pins = <
305 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
306 >;
307 };
308
309 pinctrl_ecspi1: ecspi1-grp {
310 fsl,pins = <
311 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
312 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
313 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
314 >;
315 };
316
317 pinctrl_flexcan2: flexcan2-grp {
318 fsl,pins = <
319 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
320 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
321 >;
322 };
323
324 pinctrl_gpio_bl_on: gpio-bl-on-grp {
325 fsl,pins = <
326 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
327 >;
328 };
329
330 pinctrl_gpio1: gpio1-grp {
331 fsl,pins = <
332 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
333 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
334 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
335 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
336 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
337 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */
338 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */
339 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */
340 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */
341 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */
342 >;
343 };
344
345 pinctrl_gpio2: gpio2-grp { /* Camera */
346 fsl,pins = <
347 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */
348 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */
349 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */
350 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */
351 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */
352 >;
353 };
354
355 pinctrl_gpio3: gpio3-grp { /* CAN2 */
356 fsl,pins = <
357 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */
358 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */
359 >;
360 };
361
362 pinctrl_gpio4: gpio4-grp {
363 fsl,pins = <
364 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */
365 >;
366 };
367
368 pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
369 fsl,pins = <
370 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */
371 >;
372 };
373
374 pinctrl_gpio6: gpio6-grp { /* Wifi pins */
375 fsl,pins = <
376 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */
377 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */
378 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */
379 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */
380 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */
381 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */
382 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */
383 >;
384 };
385
386 pinctrl_gpmi_nand: gpmi-nand-grp {
387 fsl,pins = <
388 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
389 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
390 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
391 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
392 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
393 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
394 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
395 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
396 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
397 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
398 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
399 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
400 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
401 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
402 >;
403 };
404
405 pinctrl_i2c1: i2c1-grp {
406 fsl,pins = <
407 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
408 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
409 >;
410 };
411
412 pinctrl_i2c1_gpio: i2c1-gpio-grp {
413 fsl,pins = <
414 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
415 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
416 >;
417 };
418
419 pinctrl_i2c2: i2c2-grp {
420 fsl,pins = <
421 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
422 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
423 >;
424 };
425
426 pinctrl_i2c2_gpio: i2c2-gpio-grp {
427 fsl,pins = <
428 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
429 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
430 >;
431 };
432
433 pinctrl_lcdif_dat: lcdif-dat-grp {
434 fsl,pins = <
435 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079
436 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079
437 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079
438 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079
439 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079
440 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079
441 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079
442 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079
443 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079
444 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079
445 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079
446 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079
447 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079
448 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079
449 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079
450 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079
451 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079
452 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079
453 >;
454 };
455
456 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
457 fsl,pins = <
458 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079
459 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079
460 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079
461 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079
462 >;
463 };
464
465 pinctrl_pwm4: pwm4-grp {
466 fsl,pins = <
467 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079
468 >;
469 };
470
471 pinctrl_pwm5: pwm5-grp {
472 fsl,pins = <
473 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079
474 >;
475 };
476
477 pinctrl_pwm6: pwm6-grp {
478 fsl,pins = <
479 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
480 >;
481 };
482
483 pinctrl_pwm7: pwm7-grp {
484 fsl,pins = <
485 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079
486 >;
487 };
488
489 pinctrl_uart1: uart1-grp {
490 fsl,pins = <
491 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1
492 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1
493 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1
494 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1
495 >;
496 };
497
498 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
499 fsl,pins = <
500 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */
501 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */
502 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
503 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */
504 >;
505 };
506
507 pinctrl_uart2: uart2-grp {
508 fsl,pins = <
509 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
510 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
511 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
512 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
513 >;
514 };
515 pinctrl_uart5: uart5-grp {
516 fsl,pins = <
517 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
518 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1
519 >;
520 };
521
522 pinctrl_usbh_reg: gpio-usbh-reg {
523 fsl,pins = <
524 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */
525 >;
526 };
527
528 pinctrl_usdhc1: usdhc1-grp {
529 fsl,pins = <
530 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
531 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
532 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
533 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
534 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
535 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
536 >;
537 };
538
539 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
540 fsl,pins = <
541 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
542 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
543 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
544 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
545 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
546 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
547 >;
548 };
549
550 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
551 fsl,pins = <
552 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
553 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
554 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
555 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
556 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
557 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
558 >;
559 };
560
561 pinctrl_usdhc2: usdhc2-grp {
562 fsl,pins = <
563 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
564 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
565 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
566 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
567 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
568 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
569
570 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
571 >;
572 };
573};
574
575&iomuxc_snvs {
576 pinctrl_snvs_gpio1: snvs-gpio1-grp {
577 fsl,pins = <
578 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */
579 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */
580 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */
581 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */
582 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */
583 >;
584 };
585
586 pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
587 fsl,pins = <
588 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */
589 >;
590 };
591
592 pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
593 fsl,pins = <
594 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */
595 >;
596 };
597
598 pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
599 fsl,pins = <
600 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
601 >;
602 };
603
604 pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
605 fsl,pins = <
606 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
607 >;
608 };
609
610 pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
611 fsl,pins = <
612 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
613 >;
614 };
615
616 pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
617 fsl,pins = <
618 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0
619 >;
620 };
621
622 pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
623 fsl,pins = <
624 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */
625 >;
626 };
627
628 pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
629 fsl,pins = <
630 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14
631 >;
632 };
633};