blob: db2e96c227df6b3df8649e12d6608e365d3c6b0e [file] [log] [blame]
wdenk3a473b22004-01-03 00:43:19 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28/*************************************************************************
29 * (c) 2002 Datentechnik AG - Project: Dino
30 *
31 *
32 * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
33 *
34 ************************************************************************/
35
36/*************************************************************************
37 *
38 * History:
39 *
40 * $Log: DB64360.h,v $
41 * Revision 1.3 2003/04/26 04:58:13 brad
42 * Cosmetic changes and compiler warning cleanups
43 *
44 * Revision 1.2 2003/04/23 15:48:15 ingo
45 * mem. map output added
46 *
47 * Revision 1.1 2003/04/17 09:31:42 ias
48 * keymile changes 17_04_2003
49 *
50 * Revision 1.10 2003/03/06 12:25:04 ias
51 * 750 FX CPU HID settings updated
52 *
53 * Revision 1.9 2003/03/03 16:14:36 ias
54 * cleanup compiler warnings of printf fuctions
55 *
56 * Revision 1.8 2003/03/03 15:11:44 ias
57 * Marvell MPSC-UART is working
58 *
59 * Revision 1.7 2003/02/26 12:15:45 ssu
60 * adapted default parameters to new board flash address
61 *
62 * Revision 1.6 2003/02/25 14:55:42 ssu
63 * changed default environment parameters
64 *
65 * Revision 1.5 2003/02/21 17:14:23 ias
66 * added extended SPD handling
67 *
68 * Revision 1.4 2003/01/14 09:16:08 ias
69 * PPCBoot for Marvel Beta 0.9
70 *
71 * Revision 1.3 2002/12/03 13:56:26 ias
72 * Environment in flash support added
73 *
74 * Revision 1.2 2002/11/29 16:53:29 ias
75 * Flash support for STM added
76 *
77 * Revision 1.1 2002/11/29 13:36:31 ias
78 * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
79 * - working DDRRAM (only 32MByte of 128MB Modul)
80 * - working I2C Driver for SPD EEPROM read
81 * - working DUART 16650 for Serial Console
82 * - working "console"
83 *
84 *
85 *
86 ************************************************************************/
87
88#ifndef __CONFIG_H
89#define __CONFIG_H
90
wdenk3a473b22004-01-03 00:43:19 +000091/* This define must be before the core.h include */
92#define CONFIG_DB64360 1 /* this is an DB64360 board */
93
94#ifndef __ASSEMBLY__
95#include "../board/Marvell/include/core.h"
96#endif
97
98/*-----------------------------------------------------*/
99/* #include "../board/db64360/local.h" */
100#ifndef __LOCAL_H
101#define __LOCAL_H
102
103/* first ethernet */
104#define CONFIG_ETHADDR 64:36:00:00:00:01
105 /* next two ethernet hwaddrs */
wdenke2ffd592004-12-31 09:32:47 +0000106#define CONFIG_HAS_ETH1
wdenk3a473b22004-01-03 00:43:19 +0000107#define CONFIG_ETH1ADDR 64:36:00:00:00:02
108/* in the atlantis 64360 we have only 2 ETH port on the board,
109if we use PCI it has its own MAC addr */
110
111#define CONFIG_ENV_OVERWRITE
112#endif /* __CONFIG_H */
113
114/*
115 * High Level Configuration Options
116 * (easy to change)
117 */
118
119#define CONFIG_74xx /* we have a 750FX (override local.h) */
120
121#define CONFIG_DB64360 1 /* this is an DB64360 board */
122
123#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
124/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
125 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
126 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
127 see sdram_init.c */
128#undef CONFIG_ECC /* enable ECC support */
129#define CONFIG_MV64360_ECC
130
131/* which initialization functions to call for this board */
132#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
wdenkc837dcb2004-01-20 23:12:12 +0000133#define CONFIG_BOARD_EARLY_INIT_F
wdenk3a473b22004-01-03 00:43:19 +0000134
135#define CFG_BOARD_NAME "DB64360"
136#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)"
137
138/*#define CFG_HUSH_PARSER */
139#undef CFG_HUSH_PARSER
140
141#define CFG_PROMPT_HUSH_PS2 "> "
142
143/*
144 * The following defines let you select what serial you want to use
145 * for your console driver.
146 *
147 * what to do:
148 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
149 * cable onto the second DUART channel, change the CFG_DUART port from 1
150 * to 0 below.
151 *
152 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
153 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
154 */
155
156#define CONFIG_MPSC_PORT 0
157
158/* to change the default ethernet port, use this define (options: 0, 1, 2) */
159#define CONFIG_NET_MULTI
160#define MV_ETH_DEVS 2
161
162/* #undef CONFIG_ETHER_PORT_MII */
163#if 0
164#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
165#else
166#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
167#endif
168#define CONFIG_ZERO_BOOTDELAY_CHECK
169
170
171#undef CONFIG_BOOTARGS
172/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
173
174/* ronen - autoboot using tftp */
175#if (CONFIG_BOOTDELAY >= 0)
176#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100177 setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
178 ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; "
wdenk3a473b22004-01-03 00:43:19 +0000179
180#define CONFIG_BOOTARGS "console=ttyS0,115200"
181
182#endif
183
184/* ronen - the u-boot.bin should be ~0x30000 bytes */
185#define CONFIG_EXTRA_ENV_SETTINGS \
186 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
187cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
188 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
189cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
190 "bootargs_root=root=/dev/nfs rw\0" \
191 "bootargs_end=:::DB64360:eth0:none \0"\
192 "ethprime=mv_enet0\0"\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100193 "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
194ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
wdenk3a473b22004-01-03 00:43:19 +0000195
196/* --------------------------------------------------------------------------------------------------------------- */
197/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
198
199#define CONFIG_IPADDR 10.2.40.90
200
201#define CONFIG_SERIAL "No. 1"
202#define CONFIG_SERVERIP 10.2.1.126
203#define CONFIG_ROOTPATH /mnt/yellow_dog_mini
204
205
206#define CONFIG_TESTDRAMDATA y
207#define CONFIG_TESTDRAMADDRESS n
208#define CONFIG_TESETDRAMWALK n
209
210/* --------------------------------------------------------------------------------------------------------------- */
211
212#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
213#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
214
215#undef CONFIG_WATCHDOG /* watchdog disabled */
216#undef CONFIG_ALTIVEC /* undef to disable */
217
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500218/*
219 * BOOTP options
220 */
221#define CONFIG_BOOTP_SUBNETMASK
222#define CONFIG_BOOTP_GATEWAY
223#define CONFIG_BOOTP_HOSTNAME
224#define CONFIG_BOOTP_BOOTPATH
225#define CONFIG_BOOTP_BOOTFILESIZE
226
227
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200228/*
229 * JFFS2 partitions
230 *
231 */
232/* No command line, one static partition, whole device */
233#undef CONFIG_JFFS2_CMDLINE
234#define CONFIG_JFFS2_DEV "nor1"
235#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
236#define CONFIG_JFFS2_PART_OFFSET 0x00000000
wdenk3a473b22004-01-03 00:43:19 +0000237
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200238/* mtdparts command line support */
239
240/* Use first bank for JFFS2, second bank contains U-Boot.
241 *
242 * Note: fake mtd_id's used, no linux mtd map file.
243 */
244/*
245#define CONFIG_JFFS2_CMDLINE
246#define MTDIDS_DEFAULT "nor1=db64360-1"
247#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)"
248*/
wdenk3a473b22004-01-03 00:43:19 +0000249
wdenk3a473b22004-01-03 00:43:19 +0000250
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500251/*
252 * Command line configuration.
253 */
254#include <config_cmd_default.h>
255
256#define CONFIG_CMD_ASKENV
257#define CONFIG_CMD_I2C
258#define CONFIG_CMD_EEPROM
259#define CONFIG_CMD_CACHE
260#define CONFIG_CMD_JFFS2
261#define CONFIG_CMD_PCI
262#define CONFIG_CMD_NET
263
wdenk3a473b22004-01-03 00:43:19 +0000264
265/*
266 * Miscellaneous configurable options
267 */
268#define CFG_I2C_EEPROM_ADDR_LEN 1
269#define CFG_I2C_MULTI_EEPROMS
270#define CFG_I2C_SPEED 40000 /* I2C speed default */
271
272/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
273#define CFG_LONGHELP /* undef to save memory */
274#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500275#if defined(CONFIG_CMD_KGDB)
wdenk3a473b22004-01-03 00:43:19 +0000276#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
277#else
278#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
279#endif
280#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
281#define CFG_MAXARGS 16 /* max number of command args */
282#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
283
284/*#define CFG_MEMTEST_START 0x00400000 memtest works on */
285/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
286/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
287
288/*
289#define CFG_DRAM_TEST
290 * DRAM tests
291 * CFG_DRAM_TEST - enables the following tests.
292 *
293 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
294 * Environment variable 'test_dram_data' must be
295 * set to 'y'.
296 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
297 * addressable. Environment variable
298 * 'test_dram_address' must be set to 'y'.
299 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
300 * This test takes about 6 minutes to test 64 MB.
301 * Environment variable 'test_dram_walk' must be
302 * set to 'y'.
303 */
304#define CFG_DRAM_TEST
305#if defined(CFG_DRAM_TEST)
306#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
307/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
308#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
309#define CFG_DRAM_TEST_DATA
310#define CFG_DRAM_TEST_ADDRESS
311#define CFG_DRAM_TEST_WALK
312#endif /* CFG_DRAM_TEST */
313
314#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
315#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
316
317#define CFG_LOAD_ADDR 0x00400000 /* default load address */
318
319#define CFG_HZ 1000 /* decr freq: 1ms ticks */
320/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
321#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
322#define CFG_BUS_CLK CFG_BUS_HZ
323
324#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
325#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
326
327/*ronen - this is the Tclk (MV64360 core) */
328#define CFG_TCLK 133000000
329
330
331#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
332
333#define CFG_750FX_HID0 0x8000c084
334#define CFG_750FX_HID1 0x54800000
335#define CFG_750FX_HID2 0x00000000
336
337/*
338 * Low Level Configuration Settings
339 * (address mappings, register initial values, etc.)
340 * You should know what you are doing if you make changes here.
341 */
342
343/*-----------------------------------------------------------------------
344 * Definitions for initial stack pointer and data area
345 */
346
347/*
348 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
349 * To an unused memory region. The stack will remain in cache until RAM
350 * is initialized
351*/
352#define CFG_INIT_RAM_LOCK
353#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */
354#define CFG_INIT_RAM_END 0x1000
355#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
356#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
357
358#define RELOCATE_INTERNAL_RAM_ADDR
359#ifdef RELOCATE_INTERNAL_RAM_ADDR
360 #define CFG_INTERNAL_RAM_ADDR 0xf8000000
361#endif
362
363/*-----------------------------------------------------------------------
364 * Start addresses for the final memory configuration
365 * (Set up by the startup code)
366 * Please note that CFG_SDRAM_BASE _must_ start at 0
367 */
368#define CFG_SDRAM_BASE 0x00000000
369/* Dummies for BAT 4-7 */
370#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
371#define CFG_SDRAM2_BASE 0x20000000
372#define CFG_SDRAM3_BASE 0x30000000
373#define CFG_SDRAM4_BASE 0x40000000
374#define CFG_FLASH_BASE 0xfff00000
375
376#define CFG_DFL_BOOTCS_BASE 0xff800000
377#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
378
379#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
380#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
381#define PCI0_IO_BASE_BOOTM 0xfd000000
382
383#define CFG_RESET_ADDRESS 0xfff00100
384#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
385#define CFG_MONITOR_BASE CFG_FLASH_BASE
386#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
387
388/* areas to map different things with the GT in physical space */
389#define CFG_DRAM_BANKS 4
390
391/* What to put in the bats. */
392#define CFG_MISC_REGION_BASE 0xf0000000
393
394/* Peripheral Device section */
395
396/*******************************************************/
397/* We have on the db64360 Board : */
398/* GT-Chipset Register Area */
399/* GT-Chipset internal SRAM 256k */
400/* SRAM on external device module */
401/* Real time clock on external device module */
402/* dobble UART on external device module */
403/* Data flash on external device module */
404/* Boot flash on external device module */
405/*******************************************************/
406#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
407#define CFG_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */
408
409/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
410#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
411#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
412
413#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
414#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
415#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
416#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
417
418#define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */
419#define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */
420#define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */
421#define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */
422/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
423
424/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
425#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
426#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
427#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
428#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
429#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
430
431 /* c 4 a 8 2 4 1 c */
432 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
433 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
434 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
435 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
436
437
438/* ronen - update MPP Control MV64360*/
439#define CFG_MPP_CONTROL_0 0x02222222
440#define CFG_MPP_CONTROL_1 0x11333011
441#define CFG_MPP_CONTROL_2 0x40431111
442#define CFG_MPP_CONTROL_3 0x00000044
443
444/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
445
446
447# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
448 /* gpp[31] gpp[30] gpp[29] gpp[28] */
449 /* gpp[27] gpp[24]*/
450 /* gpp[19:14] */
451
452/* setup new config_value for MV64360 DDR-RAM !! */
453# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
454
455#define CFG_DUART_IO CFG_DEV2_SPACE
456#define CFG_DUART_CHAN 1 /* channel to use for console */
457#define CFG_INIT_CHAN1
458#define CFG_INIT_CHAN2
459
460#define SRAM_BASE CFG_DEV0_SPACE
461#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
462
463
464/*-----------------------------------------------------------------------
465 * PCI stuff
466 *-----------------------------------------------------------------------
467 */
468
469#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
470#define PCI_HOST_FORCE 1 /* configure as pci host */
471#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
472
473#define CONFIG_PCI /* include pci support */
474#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
475#define CONFIG_PCI_PNP /* do pci plug-and-play */
476#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
477
478/* PCI MEMORY MAP section */
479#define CFG_PCI0_MEM_BASE 0x80000000
480#define CFG_PCI0_MEM_SIZE _128M
481#define CFG_PCI1_MEM_BASE 0x88000000
482#define CFG_PCI1_MEM_SIZE _128M
483
484#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
485#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
486
487/* PCI I/O MAP section */
488#define CFG_PCI0_IO_BASE 0xfa000000
489#define CFG_PCI0_IO_SIZE _16M
490#define CFG_PCI1_IO_BASE 0xfb000000
491#define CFG_PCI1_IO_SIZE _16M
492
493#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
494#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
495#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
496#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
497
498#if defined (CONFIG_750CX)
499#define CFG_PCI_IDSEL 0x0
500#else
501#define CFG_PCI_IDSEL 0x30
502#endif
503/*----------------------------------------------------------------------
504 * Initial BAT mappings
505 */
506
507/* NOTES:
508 * 1) GUARDED and WRITE_THRU not allowed in IBATS
509 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
510 */
511
512/* SDRAM */
513#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
514#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
515#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
516#define CFG_DBAT0U CFG_IBAT0U
517
518/* init ram */
519#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
520#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
521#define CFG_DBAT1L CFG_IBAT1L
522#define CFG_DBAT1U CFG_IBAT1U
523
524/* PCI0, PCI1 in one BAT */
525#define CFG_IBAT2L BATL_NO_ACCESS
526#define CFG_IBAT2U CFG_DBAT2U
527#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
528#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
529
530/* GT regs, bootrom, all the devices, PCI I/O */
531#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
532#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
533#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
534#define CFG_DBAT3U CFG_IBAT3U
535
536/* I2C addresses for the two DIMM SPD chips */
537#define DIMM0_I2C_ADDR 0x56
538#define DIMM1_I2C_ADDR 0x54
539
540/*
541 * For booting Linux, the board info and command line data
542 * have to be in the first 8 MB of memory, since this is
543 * the maximum mapped by the Linux kernel during initialization.
544 */
545#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
546
547/*-----------------------------------------------------------------------
548 * FLASH organization
549 */
550#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
551#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
552
553#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
554#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
555#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */
556
557#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
558#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
559#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
560#define CFG_FLASH_CFI 1
561
562#define CFG_ENV_IS_IN_FLASH 1
563#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
564#define CFG_ENV_SECT_SIZE 0x10000
565#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
566/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
567
568/*-----------------------------------------------------------------------
569 * Cache Configuration
570 */
571#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500572#if defined(CONFIG_CMD_KGDB)
wdenk3a473b22004-01-03 00:43:19 +0000573#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
574#endif
575
576/*-----------------------------------------------------------------------
577 * L2CR setup -- make sure this is right for your board!
578 * look in include/mpc74xx.h for the defines used here
579 */
580
581#define CFG_L2
582
583
584#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
585#define L2_INIT 0
586#else
587
588#define L2_INIT 0
589/*
590#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
591 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
592*/
593#endif
594
595#define L2_ENABLE (L2_INIT | L2CR_L2E)
596
597/*
598 * Internal Definitions
599 *
600 * Boot Flags
601 */
602#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
603#define BOOTFLAG_WARM 0x02 /* Software reboot */
604
605#define CFG_BOARD_ASM_INIT 1
606
607#endif /* __CONFIG_H */