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Mingkai Hu4f1d1b72011-07-07 12:29:15 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
Tom Rini5b8031c2016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08005 */
6
7#include <common.h>
8#include <i2c.h>
9#include <hwconfig.h>
10#include <asm/mmu.h>
York Sun5614e712013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
12#include <fsl_ddr_dimm_params.h>
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080013#include <asm/fsl_law.h>
14
York Sun712cf7a2011-10-03 09:19:53 -070015struct board_specific_parameters {
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080016 u32 n_ranks;
York Sun712cf7a2011-10-03 09:19:53 -070017 u32 datarate_mhz_high;
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080018 u32 clk_adjust;
19 u32 wrlvl_start;
20 u32 cpo;
21 u32 write_data_delay;
Priyanka Jain0dd38a32013-09-25 10:41:19 +053022 u32 force_2t;
York Sun712cf7a2011-10-03 09:19:53 -070023};
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080024
25/*
York Sun712cf7a2011-10-03 09:19:53 -070026 * This table contains all valid speeds we want to override with board
27 * specific parameters. datarate_mhz_high values need to be in ascending order
28 * for each n_ranks group.
29 *
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080030 * ranges for parameters:
31 * wr_data_delay = 0-6
32 * clk adjust = 0-8
33 * cpo 2-0x1E (30)
34 */
York Sun712cf7a2011-10-03 09:19:53 -070035static const struct board_specific_parameters dimm0[] = {
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080036 /*
37 * memory controller 0
York Sun712cf7a2011-10-03 09:19:53 -070038 * num| hi| clk| wrlvl | cpo |wrdata|2T
39 * ranks| mhz|adjst| start | delay|
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080040 */
York Sun712cf7a2011-10-03 09:19:53 -070041 {2, 750, 3, 5, 0xff, 2, 0},
42 {2, 1250, 4, 6, 0xff, 2, 0},
43 {2, 1350, 5, 7, 0xff, 2, 0},
44 {2, 1666, 5, 8, 0xff, 2, 0},
45 {}
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080046};
47
48void fsl_ddr_board_options(memctl_options_t *popts,
49 dimm_params_t *pdimm,
50 unsigned int ctrl_num)
51{
York Sun712cf7a2011-10-03 09:19:53 -070052 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080053 ulong ddr_freq;
54
York Sun712cf7a2011-10-03 09:19:53 -070055 if (ctrl_num) {
56 printf("Wrong parameter for controller number %d", ctrl_num);
57 return;
58 }
59 if (!pdimm->n_ranks)
60 return;
61
62 pbsp = dimm0;
63
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080064 /*
65 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
66 * freqency and n_banks specified in board_specific_parameters table.
67 */
68 ddr_freq = get_ddr_freq(0) / 1000000;
York Sun712cf7a2011-10-03 09:19:53 -070069 while (pbsp->datarate_mhz_high) {
70 if (pbsp->n_ranks == pdimm->n_ranks) {
71 if (ddr_freq <= pbsp->datarate_mhz_high) {
72 popts->cpo_override = pbsp->cpo;
73 popts->write_data_delay =
74 pbsp->write_data_delay;
75 popts->clk_adjust = pbsp->clk_adjust;
76 popts->wrlvl_start = pbsp->wrlvl_start;
Priyanka Jain0dd38a32013-09-25 10:41:19 +053077 popts->twot_en = pbsp->force_2t;
York Sun712cf7a2011-10-03 09:19:53 -070078 goto found;
79 }
80 pbsp_highest = pbsp;
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080081 }
82 pbsp++;
83 }
84
York Sun712cf7a2011-10-03 09:19:53 -070085 if (pbsp_highest) {
86 printf("Error: board specific timing not found "
87 "for data rate %lu MT/s!\n"
88 "Trying to use the highest speed (%u) parameters\n",
89 ddr_freq, pbsp_highest->datarate_mhz_high);
90 popts->cpo_override = pbsp_highest->cpo;
91 popts->write_data_delay = pbsp_highest->write_data_delay;
92 popts->clk_adjust = pbsp_highest->clk_adjust;
93 popts->wrlvl_start = pbsp_highest->wrlvl_start;
Priyanka Jain0dd38a32013-09-25 10:41:19 +053094 popts->twot_en = pbsp_highest->force_2t;
York Sun712cf7a2011-10-03 09:19:53 -070095 } else {
96 panic("DIMM is not supported by this board");
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080097 }
98
York Sun712cf7a2011-10-03 09:19:53 -070099found:
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800100 /*
101 * Factors to consider for half-strength driver enable:
102 * - number of DIMMs installed
103 */
104 popts->half_strength_driver_enable = 0;
105 /* Write leveling override */
106 popts->wrlvl_override = 1;
107 popts->wrlvl_sample = 0xf;
108
109 /* Rtt and Rtt_WR override */
110 popts->rtt_override = 0;
111
112 /* Enable ZQ calibration */
113 popts->zq_en = 1;
114
115 /* DHC_EN =1, ODT = 60 Ohm */
116 popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
117}
118
119phys_size_t initdram(int board_type)
120{
121 phys_size_t dram_size = 0;
122
123 puts("Initializing....");
124
125 if (fsl_use_spd()) {
126 puts("using SPD\n");
127 dram_size = fsl_ddr_sdram();
128 } else {
129 puts("no SPD and fixed parameters\n");
130 return dram_size;
131 }
132
133 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
134 dram_size *= 0x100000;
135
Wolfgang Denk21cd5812011-07-25 10:13:53 +0200136 debug(" DDR: ");
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800137 return dram_size;
138}