blob: a6143df4c063df9333f42304d67f8359ff82ffad [file] [log] [blame]
Gary Jennejohn041a2552007-08-31 14:29:04 +02001/*
2 * (C) Copyright 2007
3 * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24/* sil680.c - ide support functions for the Sil0680A controller */
25
26/*
27 * The following parameters must be defined in the configuration file
28 * of the target board:
29 *
30 * #define CFG_IDE_SIL680
31 *
32 * #define CONFIG_PCI_PNP
33 * NOTE it may also be necessary to define this if the default of 8 is
34 * incorrect for the target board (e.g. the sequoia board requires 0).
35 * #define CFG_PCI_CACHE_LINE_SIZE 0
36 *
37 * #define CONFIG_CMD_IDE
38 * #undef CONFIG_IDE_8xx_DIRECT
39 * #undef CONFIG_IDE_LED
40 * #undef CONFIG_IDE_RESET
41 * #define CONFIG_IDE_PREINIT
42 * #define CFG_IDE_MAXBUS 2 - modify to suit
43 * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit
44 * #define CFG_ATA_BASE_ADDR 0
45 * #define CFG_ATA_IDE0_OFFSET 0
46 * #define CFG_ATA_IDE1_OFFSET 0
47 * #define CFG_ATA_DATA_OFFSET 0
48 * #define CFG_ATA_REG_OFFSET 0
49 * #define CFG_ATA_ALT_OFFSET 0x0004
50 *
51 * The mapping for PCI IO-space.
52 * NOTE this is the value for the sequoia board. Modify to suit.
53 * #define CFG_PCI0_IO_SPACE 0xE8000000
54 */
55
56#include <common.h>
57#if defined(CFG_IDE_SIL680)
58#include <ata.h>
59#include <ide.h>
60#include <pci.h>
61
62extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
63
64int ide_preinit (void)
65{
66 int status;
67 pci_dev_t devbusfn;
68 int l;
69
70 status = 1;
71 for (l = 0; l < CFG_IDE_MAXBUS; l++) {
72 ide_bus_offset[l] = -ATA_STATUS;
73 }
74 devbusfn = pci_find_device (0x1095, 0x0680, 0);
75 if (devbusfn != -1) {
76 status = 0;
77
78 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
79 (u32 *) &ide_bus_offset[0]);
80 ide_bus_offset[0] &= 0xfffffff8;
81 ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
82 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
83 (u32 *) &ide_bus_offset[1]);
84 ide_bus_offset[1] &= 0xfffffff8;
85 ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
86 /* init various things - taken from the Linux driver */
87 /* set PIO mode */
88 pci_write_config_byte(devbusfn, 0x80, 0x00);
89 pci_write_config_byte(devbusfn, 0x84, 0x00);
90 /* IDE0 */
91 pci_write_config_byte(devbusfn, 0xA1, 0x02);
92 pci_write_config_word(devbusfn, 0xA2, 0x328A);
93 pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
94 pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
95 pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
96 /* IDE1 */
97 pci_write_config_byte(devbusfn, 0xB1, 0x02);
98 pci_write_config_word(devbusfn, 0xB2, 0x328A);
99 pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
100 pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
101 pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
102 }
103 return (status);
104}
105
106void ide_set_reset (int flag) {
107 return;
108}
109
110#endif /* CFG_IDE_SIL680 */