blob: 29a3e61e80303db9e66b5b2c9e3e8868e5ef520e [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
Wolfgang Denk8cba0902006-05-12 16:15:46 +02005 * (C) Copyright 2000-2006
wdenkd4ca31c2004-01-02 14:00:00 +00006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
wdenkfe8c2802002-11-03 00:38:21 +00008 * This file contains structures and information for the communication
9 * processor channels. Some CPM control and status is available
10 * throught the MPC8xx internal memory map. See immap.h for details.
11 * This file only contains what I need for the moment, not the total
12 * CPM capabilities. I (or someone else) will add definitions as they
13 * are needed. -- Dan
14 *
wdenkfe8c2802002-11-03 00:38:21 +000015 */
16#ifndef __CPM_8XX__
17#define __CPM_8XX__
18
wdenkfe8c2802002-11-03 00:38:21 +000019#include <asm/8xx_immap.h>
20
21/* CPM Command register.
22*/
wdenk7c7a23b2002-12-07 00:20:59 +000023#define CPM_CR_RST ((ushort)0x8000)
24#define CPM_CR_OPCODE ((ushort)0x0f00)
25#define CPM_CR_CHAN ((ushort)0x00f0)
26#define CPM_CR_FLG ((ushort)0x0001)
wdenkfe8c2802002-11-03 00:38:21 +000027
28/* Some commands (there are more...later)
29*/
30#define CPM_CR_INIT_TRX ((ushort)0x0000)
31#define CPM_CR_INIT_RX ((ushort)0x0001)
32#define CPM_CR_INIT_TX ((ushort)0x0002)
33#define CPM_CR_HUNT_MODE ((ushort)0x0003)
34#define CPM_CR_STOP_TX ((ushort)0x0004)
35#define CPM_CR_RESTART_TX ((ushort)0x0006)
36#define CPM_CR_SET_GADDR ((ushort)0x0008)
37
38/* Channel numbers.
39*/
wdenk7c7a23b2002-12-07 00:20:59 +000040#define CPM_CR_CH_SCC1 ((ushort)0x0000)
41#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
42#define CPM_CR_CH_SCC2 ((ushort)0x0004)
43#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
44#define CPM_CR_CH_SCC3 ((ushort)0x0008)
45#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
46#define CPM_CR_CH_SCC4 ((ushort)0x000c)
47#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
wdenkfe8c2802002-11-03 00:38:21 +000048
49#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
50
51/*
52 * DPRAM defines and allocation functions
53 */
54
55/* The dual ported RAM is multi-functional. Some areas can be (and are
56 * being) used for microcode. There is an area that can only be used
57 * as data ram for buffer descriptors, which is all we use right now.
58 * Currently the first 512 and last 256 bytes are used for microcode.
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#ifdef CONFIG_SYS_ALLOC_DPRAM
wdenkfe8c2802002-11-03 00:38:21 +000061
62#define CPM_DATAONLY_BASE ((uint)0x0800)
63#define CPM_DATAONLY_SIZE ((uint)0x0700)
64#define CPM_DP_NOSPACE ((uint)0x7fffffff)
65
66#else
67
68#define CPM_SERIAL_BASE 0x0800
69#define CPM_I2C_BASE 0x0820
70#define CPM_SPI_BASE 0x0840
71#define CPM_FEC_BASE 0x0860
wdenk79536a62004-09-27 20:20:11 +000072#define CPM_SERIAL2_BASE 0x08E0
wdenkfe8c2802002-11-03 00:38:21 +000073#define CPM_SCC_BASE 0x0900
74#define CPM_POST_BASE 0x0980
wdenk281e00a2004-08-01 22:48:16 +000075#define CPM_WLKBD_BASE 0x0a00
wdenkfe8c2802002-11-03 00:38:21 +000076
77#endif
78
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
wdenkfe8c2802002-11-03 00:38:21 +000080#define CPM_POST_WORD_ADDR 0x07FC
wdenkea909b72002-11-21 23:11:29 +000081#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
wdenkea909b72002-11-21 23:11:29 +000083#endif
wdenkfe8c2802002-11-03 00:38:21 +000084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
wdenkbdccc4f2003-08-05 17:43:17 +000086#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
87#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
wdenkbdccc4f2003-08-05 17:43:17 +000089#endif
90
wdenkfe8c2802002-11-03 00:38:21 +000091#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
92
93/* Export the base address of the communication processor registers
94 * and dual port ram.
95 */
96extern cpm8xx_t *cpmp; /* Pointer to comm processor */
97
98/* Buffer descriptors used by many of the CPM protocols.
99*/
100typedef struct cpm_buf_desc {
101 ushort cbd_sc; /* Status and Control */
102 ushort cbd_datlen; /* Data length in buffer */
103 uint cbd_bufaddr; /* Buffer address in host memory */
104} cbd_t;
105
Mike Williams16263082011-07-22 04:01:30 +0000106#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
wdenkfe8c2802002-11-03 00:38:21 +0000107#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
108#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
109#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
110#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
111#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
112#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
113#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
114#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
115#define BD_SC_BR ((ushort)0x0020) /* Break received */
116#define BD_SC_FR ((ushort)0x0010) /* Framing error */
117#define BD_SC_PR ((ushort)0x0008) /* Parity error */
118#define BD_SC_OV ((ushort)0x0002) /* Overrun */
119#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
120
121/* Parameter RAM offsets.
122*/
123#define PROFF_SCC1 ((uint)0x0000)
124#define PROFF_IIC ((uint)0x0080)
Scott Wooda166fbc2013-05-17 20:01:54 -0500125#define PROFF_REVNUM ((uint)0x00b0)
wdenkfe8c2802002-11-03 00:38:21 +0000126#define PROFF_SCC2 ((uint)0x0100)
127#define PROFF_SPI ((uint)0x0180)
128#define PROFF_SCC3 ((uint)0x0200)
129#define PROFF_SMC1 ((uint)0x0280)
130#define PROFF_SCC4 ((uint)0x0300)
131#define PROFF_SMC2 ((uint)0x0380)
132
133/* Define enough so I can at least use the serial port as a UART.
wdenkfe8c2802002-11-03 00:38:21 +0000134 */
135typedef struct smc_uart {
136 ushort smc_rbase; /* Rx Buffer descriptor base address */
137 ushort smc_tbase; /* Tx Buffer descriptor base address */
138 u_char smc_rfcr; /* Rx function code */
139 u_char smc_tfcr; /* Tx function code */
140 ushort smc_mrblr; /* Max receive buffer length */
141 uint smc_rstate; /* Internal */
142 uint smc_idp; /* Internal */
143 ushort smc_rbptr; /* Internal */
144 ushort smc_ibc; /* Internal */
145 uint smc_rxtmp; /* Internal */
146 uint smc_tstate; /* Internal */
147 uint smc_tdp; /* Internal */
148 ushort smc_tbptr; /* Internal */
149 ushort smc_tbc; /* Internal */
150 uint smc_txtmp; /* Internal */
151 ushort smc_maxidl; /* Maximum idle characters */
152 ushort smc_tmpidl; /* Temporary idle counter */
153 ushort smc_brklen; /* Last received break length */
154 ushort smc_brkec; /* rcv'd break condition counter */
155 ushort smc_brkcr; /* xmt break count register */
156 ushort smc_rmask; /* Temporary bit mask */
Heiko Schocherb423d052008-01-11 01:12:07 +0100157 u_char res1[8];
158 ushort smc_rpbase; /* Relocation pointer */
wdenkfe8c2802002-11-03 00:38:21 +0000159} smc_uart_t;
160
161/* Function code bits.
162*/
163#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
164
165/* SMC uart mode register.
166*/
167#define SMCMR_REN ((ushort)0x0001)
168#define SMCMR_TEN ((ushort)0x0002)
169#define SMCMR_DM ((ushort)0x000c)
170#define SMCMR_SM_GCI ((ushort)0x0000)
171#define SMCMR_SM_UART ((ushort)0x0020)
172#define SMCMR_SM_TRANS ((ushort)0x0030)
173#define SMCMR_SM_MASK ((ushort)0x0030)
174#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
175#define SMCMR_REVD SMCMR_PM_EVEN
176#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
177#define SMCMR_BS SMCMR_PEN
178#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
179#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
180#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
181
182/* SMC2 as Centronics parallel printer. It is half duplex, in that
183 * it can only receive or transmit. The parameter ram values for
184 * each direction are either unique or properly overlap, so we can
185 * include them in one structure.
186 */
187typedef struct smc_centronics {
188 ushort scent_rbase;
189 ushort scent_tbase;
190 u_char scent_cfcr;
191 u_char scent_smask;
192 ushort scent_mrblr;
193 uint scent_rstate;
194 uint scent_r_ptr;
195 ushort scent_rbptr;
196 ushort scent_r_cnt;
197 uint scent_rtemp;
198 uint scent_tstate;
199 uint scent_t_ptr;
200 ushort scent_tbptr;
201 ushort scent_t_cnt;
202 uint scent_ttemp;
203 ushort scent_max_sl;
204 ushort scent_sl_cnt;
205 ushort scent_character1;
206 ushort scent_character2;
207 ushort scent_character3;
208 ushort scent_character4;
209 ushort scent_character5;
210 ushort scent_character6;
211 ushort scent_character7;
212 ushort scent_character8;
213 ushort scent_rccm;
214 ushort scent_rccr;
215} smc_cent_t;
216
217/* Centronics Status Mask Register.
218*/
219#define SMC_CENT_F ((u_char)0x08)
220#define SMC_CENT_PE ((u_char)0x04)
221#define SMC_CENT_S ((u_char)0x02)
222
223/* SMC Event and Mask register.
224*/
225#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
226#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
227#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
228#define SMCM_BSY ((unsigned char)0x04)
229#define SMCM_TX ((unsigned char)0x02)
230#define SMCM_RX ((unsigned char)0x01)
231
232/* Baud rate generators.
233*/
234#define CPM_BRG_RST ((uint)0x00020000)
235#define CPM_BRG_EN ((uint)0x00010000)
236#define CPM_BRG_EXTC_INT ((uint)0x00000000)
237#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
238#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
239#define CPM_BRG_ATB ((uint)0x00002000)
240#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
241#define CPM_BRG_DIV16 ((uint)0x00000001)
242
243/* SI Clock Route Register
244*/
245#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
246#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
247#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
248#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
249#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
250#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
251#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
252#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
253
254/* SCCs.
255*/
256#define SCC_GSMRH_IRP ((uint)0x00040000)
257#define SCC_GSMRH_GDE ((uint)0x00010000)
258#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
259#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
260#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
261#define SCC_GSMRH_REVD ((uint)0x00002000)
262#define SCC_GSMRH_TRX ((uint)0x00001000)
263#define SCC_GSMRH_TTX ((uint)0x00000800)
264#define SCC_GSMRH_CDP ((uint)0x00000400)
265#define SCC_GSMRH_CTSP ((uint)0x00000200)
266#define SCC_GSMRH_CDS ((uint)0x00000100)
267#define SCC_GSMRH_CTSS ((uint)0x00000080)
268#define SCC_GSMRH_TFL ((uint)0x00000040)
269#define SCC_GSMRH_RFW ((uint)0x00000020)
270#define SCC_GSMRH_TXSY ((uint)0x00000010)
271#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
272#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
273#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
274#define SCC_GSMRH_RTSM ((uint)0x00000002)
275#define SCC_GSMRH_RSYN ((uint)0x00000001)
276
277#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
278#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
279#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
280#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
281#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
282#define SCC_GSMRL_TCI ((uint)0x10000000)
283#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
284#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
285#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
286#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
287#define SCC_GSMRL_RINV ((uint)0x02000000)
288#define SCC_GSMRL_TINV ((uint)0x01000000)
289#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
290#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
291#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
292#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
293#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
294#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
295#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
296#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
297#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
298#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
299#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
300#define SCC_GSMRL_TEND ((uint)0x00040000)
301#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
302#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
303#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
304#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
305#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
306#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
307#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
308#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
309#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
310#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
311#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
312#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
313#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
314#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
315#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
316#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
317#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
318#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
319#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
320#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
321#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
322#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
323#define SCC_GSMRL_ENR ((uint)0x00000020)
324#define SCC_GSMRL_ENT ((uint)0x00000010)
325#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
326#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
327#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
328#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
329#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
330#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
331#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
332#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
333#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
334#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
335
336#define SCC_TODR_TOD ((ushort)0x8000)
337
338/* SCC Event and Mask register.
339*/
340#define SCCM_TXE ((unsigned char)0x10)
341#define SCCM_BSY ((unsigned char)0x04)
342#define SCCM_TX ((unsigned char)0x02)
343#define SCCM_RX ((unsigned char)0x01)
344
345typedef struct scc_param {
346 ushort scc_rbase; /* Rx Buffer descriptor base address */
347 ushort scc_tbase; /* Tx Buffer descriptor base address */
348 u_char scc_rfcr; /* Rx function code */
349 u_char scc_tfcr; /* Tx function code */
350 ushort scc_mrblr; /* Max receive buffer length */
351 uint scc_rstate; /* Internal */
352 uint scc_idp; /* Internal */
353 ushort scc_rbptr; /* Internal */
354 ushort scc_ibc; /* Internal */
355 uint scc_rxtmp; /* Internal */
356 uint scc_tstate; /* Internal */
357 uint scc_tdp; /* Internal */
358 ushort scc_tbptr; /* Internal */
359 ushort scc_tbc; /* Internal */
360 uint scc_txtmp; /* Internal */
361 uint scc_rcrc; /* Internal */
362 uint scc_tcrc; /* Internal */
363} sccp_t;
364
365/* Function code bits.
366*/
367#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
368
369/* CPM Ethernet through SCCx.
370 */
371typedef struct scc_enet {
372 sccp_t sen_genscc;
373 uint sen_cpres; /* Preset CRC */
374 uint sen_cmask; /* Constant mask for CRC */
375 uint sen_crcec; /* CRC Error counter */
376 uint sen_alec; /* alignment error counter */
377 uint sen_disfc; /* discard frame counter */
378 ushort sen_pads; /* Tx short frame pad character */
379 ushort sen_retlim; /* Retry limit threshold */
380 ushort sen_retcnt; /* Retry limit counter */
381 ushort sen_maxflr; /* maximum frame length register */
382 ushort sen_minflr; /* minimum frame length register */
383 ushort sen_maxd1; /* maximum DMA1 length */
384 ushort sen_maxd2; /* maximum DMA2 length */
385 ushort sen_maxd; /* Rx max DMA */
386 ushort sen_dmacnt; /* Rx DMA counter */
387 ushort sen_maxb; /* Max BD byte count */
388 ushort sen_gaddr1; /* Group address filter */
389 ushort sen_gaddr2;
390 ushort sen_gaddr3;
391 ushort sen_gaddr4;
392 uint sen_tbuf0data0; /* Save area 0 - current frame */
393 uint sen_tbuf0data1; /* Save area 1 - current frame */
394 uint sen_tbuf0rba; /* Internal */
395 uint sen_tbuf0crc; /* Internal */
396 ushort sen_tbuf0bcnt; /* Internal */
397 ushort sen_paddrh; /* physical address (MSB) */
398 ushort sen_paddrm;
399 ushort sen_paddrl; /* physical address (LSB) */
400 ushort sen_pper; /* persistence */
401 ushort sen_rfbdptr; /* Rx first BD pointer */
402 ushort sen_tfbdptr; /* Tx first BD pointer */
403 ushort sen_tlbdptr; /* Tx last BD pointer */
404 uint sen_tbuf1data0; /* Save area 0 - current frame */
405 uint sen_tbuf1data1; /* Save area 1 - current frame */
406 uint sen_tbuf1rba; /* Internal */
407 uint sen_tbuf1crc; /* Internal */
408 ushort sen_tbuf1bcnt; /* Internal */
409 ushort sen_txlen; /* Tx Frame length counter */
410 ushort sen_iaddr1; /* Individual address filter */
411 ushort sen_iaddr2;
412 ushort sen_iaddr3;
413 ushort sen_iaddr4;
414 ushort sen_boffcnt; /* Backoff counter */
415
416 /* NOTE: Some versions of the manual have the following items
417 * incorrectly documented. Below is the proper order.
418 */
419 ushort sen_taddrh; /* temp address (MSB) */
420 ushort sen_taddrm;
421 ushort sen_taddrl; /* temp address (LSB) */
422} scc_enet_t;
423
424/**********************************************************************
425 *
426 * Board specific configuration settings.
427 *
428 * Please note that we use the presence of a #define SCC_ENET and/or
429 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
430 **********************************************************************/
431
wdenkfe8c2802002-11-03 00:38:21 +0000432/*** BSEIP **********************************************************/
433
434#ifdef CONFIG_BSEIP
435/* This ENET stuff is for the MPC823 with ethernet on SCC2.
436 * This is unique to the BSE ip-Engine board.
437 */
438#define PROFF_ENET PROFF_SCC2
439#define CPM_CR_ENET CPM_CR_CH_SCC2
440#define SCC_ENET 1
441#define PA_ENET_RXD ((ushort)0x0004)
442#define PA_ENET_TXD ((ushort)0x0008)
443#define PA_ENET_TCLK ((ushort)0x0100)
444#define PA_ENET_RCLK ((ushort)0x0200)
445#define PB_ENET_TENA ((uint)0x00002000)
446#define PC_ENET_CLSN ((ushort)0x0040)
447#define PC_ENET_RENA ((ushort)0x0080)
448
449/* BSE uses port B and C bits for PHY control also.
450*/
451#define PB_BSE_POWERUP ((uint)0x00000004)
452#define PB_BSE_FDXDIS ((uint)0x00008000)
453#define PC_BSE_LOOPBACK ((ushort)0x0800)
454
455#define SICR_ENET_MASK ((uint)0x0000ff00)
456#define SICR_ENET_CLKRT ((uint)0x00002c00)
457#endif /* CONFIG_BSEIP */
458
459/*** BSEIP **********************************************************/
460
461#ifdef CONFIG_FLAGADM
462/* Enet configuration for the FLAGADM */
463/* Enet on SCC2 */
464
465#define PROFF_ENET PROFF_SCC2
466#define CPM_CR_ENET CPM_CR_CH_SCC2
467#define SCC_ENET 1
wdenk7c7a23b2002-12-07 00:20:59 +0000468#define PA_ENET_RXD ((ushort)0x0004)
469#define PA_ENET_TXD ((ushort)0x0008)
wdenkfe8c2802002-11-03 00:38:21 +0000470#define PA_ENET_TCLK ((ushort)0x0100)
471#define PA_ENET_RCLK ((ushort)0x0400)
472#define PB_ENET_TENA ((uint)0x00002000)
473#define PC_ENET_CLSN ((ushort)0x0040)
474#define PC_ENET_RENA ((ushort)0x0080)
475
476#define SICR_ENET_MASK ((uint)0x0000ff00)
477#define SICR_ENET_CLKRT ((uint)0x00003400)
478#endif /* CONFIG_FLAGADM */
479
wdenk3bac3512003-03-12 10:41:04 +0000480/*** ELPT860 *********************************************************/
481
482#ifdef CONFIG_ELPT860
483/* Bits in parallel I/O port registers that have to be set/cleared
484 * to configure the pins for SCC1 use.
485 */
486# define PROFF_ENET PROFF_SCC1
487# define CPM_CR_ENET CPM_CR_CH_SCC1
488# define SCC_ENET 0
489
490# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
491# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
492# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
493# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
494
495# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
496# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
497# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
498
499/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
500 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
501 */
502# define SICR_ENET_MASK ((uint)0x000000FF)
503# define SICR_ENET_CLKRT ((uint)0x00000025)
504#endif /* CONFIG_ELPT860 */
505
wdenkfe8c2802002-11-03 00:38:21 +0000506/*** ESTEEM 192E **************************************************/
507#ifdef CONFIG_ESTEEM192E
508/* ESTEEM192E
509 * This ENET stuff is for the MPC850 with ethernet on SCC2. This
510 * is very similar to the RPX-Lite configuration.
511 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
512 */
513
514#define PROFF_ENET PROFF_SCC2
515#define CPM_CR_ENET CPM_CR_CH_SCC2
516#define SCC_ENET 1
517
518#define PA_ENET_RXD ((ushort)0x0004)
519#define PA_ENET_TXD ((ushort)0x0008)
520#define PA_ENET_TCLK ((ushort)0x0200)
521#define PA_ENET_RCLK ((ushort)0x0800)
522#define PB_ENET_TENA ((uint)0x00002000)
523#define PC_ENET_CLSN ((ushort)0x0040)
524#define PC_ENET_RENA ((ushort)0x0080)
525
526#define SICR_ENET_MASK ((uint)0x0000ff00)
527#define SICR_ENET_CLKRT ((uint)0x00003d00)
528
529#define PB_ENET_LOOPBACK ((uint)0x00004000)
530#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
531
532#endif
533
wdenkfe8c2802002-11-03 00:38:21 +0000534/*** FADS860T********************************************************/
535
wdenk180d3f72004-01-04 16:28:35 +0000536#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
537/*
538 * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
wdenkfe8c2802002-11-03 00:38:21 +0000539 */
wdenkfe8c2802002-11-03 00:38:21 +0000540#ifdef CONFIG_SCC1_ENET
wdenk180d3f72004-01-04 16:28:35 +0000541
wdenkfe8c2802002-11-03 00:38:21 +0000542#define SCC_ENET 0
wdenk180d3f72004-01-04 16:28:35 +0000543
wdenkfe8c2802002-11-03 00:38:21 +0000544#define PROFF_ENET PROFF_SCC1
545#define CPM_CR_ENET CPM_CR_CH_SCC1
546
547#define PA_ENET_RXD ((ushort)0x0001)
548#define PA_ENET_TXD ((ushort)0x0002)
549#define PA_ENET_TCLK ((ushort)0x0100)
550#define PA_ENET_RCLK ((ushort)0x0200)
551
552#define PB_ENET_TENA ((uint)0x00001000)
553
554#define PC_ENET_CLSN ((ushort)0x0010)
555#define PC_ENET_RENA ((ushort)0x0020)
556
557#define SICR_ENET_MASK ((uint)0x000000ff)
558#define SICR_ENET_CLKRT ((uint)0x0000002c)
559
wdenk180d3f72004-01-04 16:28:35 +0000560#endif /* CONFIG_SCC1_ETHERNET */
561
562/*
wdenk11142572004-06-06 21:35:06 +0000563 * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
564 * with ethernet on FEC.
wdenkfe8c2802002-11-03 00:38:21 +0000565 */
566
567#ifdef CONFIG_FEC_ENET
wdenk180d3f72004-01-04 16:28:35 +0000568#define FEC_ENET /* Use FEC for Ethernet */
569#endif /* CONFIG_FEC_ENET */
wdenkfe8c2802002-11-03 00:38:21 +0000570
wdenk180d3f72004-01-04 16:28:35 +0000571#endif /* CONFIG_FADS && CONFIG_MPC86x */
wdenkfe8c2802002-11-03 00:38:21 +0000572
wdenk384ae022002-11-05 00:17:55 +0000573/*** FPS850L, FPS860L ************************************************/
wdenkfe8c2802002-11-03 00:38:21 +0000574
wdenk384ae022002-11-05 00:17:55 +0000575#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
wdenkfe8c2802002-11-03 00:38:21 +0000576/* Bits in parallel I/O port registers that have to be set/cleared
wdenk384ae022002-11-05 00:17:55 +0000577 * to configure the pins for SCC2 use.
wdenkfe8c2802002-11-03 00:38:21 +0000578 */
579#define PROFF_ENET PROFF_SCC2
580#define CPM_CR_ENET CPM_CR_CH_SCC2
581#define SCC_ENET 1
582#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
583#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
584#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
585#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
586
587#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
588#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
589#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
590
591/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
592 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
593 */
594#define SICR_ENET_MASK ((uint)0x0000ff00)
595#define SICR_ENET_CLKRT ((uint)0x00002600)
wdenk384ae022002-11-05 00:17:55 +0000596#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
wdenkfe8c2802002-11-03 00:38:21 +0000597
598/*** GEN860T **********************************************************/
599#if defined(CONFIG_GEN860T)
600#undef SCC_ENET
601#define FEC_ENET
602
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200603#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
604#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
605#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
606#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
607#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
608#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
609#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
610#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
611#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
612#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
613#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
614#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
615#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
wdenkfe8c2802002-11-03 00:38:21 +0000616#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
617#endif /* CONFIG_GEN860T */
618
wdenkfe8c2802002-11-03 00:38:21 +0000619/*** HERMES-PRO ******************************************************/
620
621/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
622
623#ifdef CONFIG_HERMES
624
625#define FEC_ENET /* use FEC for EThernet */
626#undef SCC_ENET
627
628
629#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
630#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
631#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
632#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
633#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
634#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
635#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
636#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
637#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
638#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
639#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
640#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
641#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
642
643#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
644
645#endif /* CONFIG_HERMES */
646
wdenkfe8c2802002-11-03 00:38:21 +0000647/*** ICU862 **********************************************************/
648
649#if defined(CONFIG_ICU862)
650
651#ifdef CONFIG_FEC_ENET
652#define FEC_ENET /* use FEC for EThernet */
653#endif /* CONFIG_FEC_ETHERNET */
654
655#endif /* CONFIG_ICU862 */
656
657/*** IP860 **********************************************************/
658
659#if defined(CONFIG_IP860)
660/* Bits in parallel I/O port registers that have to be set/cleared
661 * to configure the pins for SCC1 use.
662 */
663#define PROFF_ENET PROFF_SCC1
664#define CPM_CR_ENET CPM_CR_CH_SCC1
665#define SCC_ENET 0
666#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
667#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
668#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
669#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
670
671#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
672#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
673#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
674
675#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
676#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
677
678/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
679 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
680 */
681#define SICR_ENET_MASK ((uint)0x000000ff)
682#define SICR_ENET_CLKRT ((uint)0x0000002C)
683#endif /* CONFIG_IP860 */
684
685/*** IVMS8 **********************************************************/
686
687/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
688
689#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
690
691#define FEC_ENET /* use FEC for EThernet */
692#undef SCC_ENET
693
694#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
695
696#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
697
698#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
699#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
700#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
701#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
702#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
703#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
704#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
705#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
706#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
707#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
708#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
709#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
710#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
711
712#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
713
714#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
715
wdenk0608e042004-03-25 19:29:38 +0000716/*** KUP4K, KUP4X ****************************************************/
717/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
wdenk56f94be2002-11-05 16:35:14 +0000718
wdenk0608e042004-03-25 19:29:38 +0000719#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
wdenk56f94be2002-11-05 16:35:14 +0000720
721#define FEC_ENET /* use FEC for EThernet */
722#undef SCC_ENET
723
724#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
725
726#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
727
728#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
729#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
730#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
731#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
732#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
733#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
734#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
735#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
736#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
737#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
738#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
739#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
740#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
741
742#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
743
744#endif /* CONFIG_KUP4K */
745
wdenkfe8c2802002-11-03 00:38:21 +0000746/*** LWMON **********************************************************/
747
wdenk281e00a2004-08-01 22:48:16 +0000748#if defined(CONFIG_LWMON)
wdenkfe8c2802002-11-03 00:38:21 +0000749/* Bits in parallel I/O port registers that have to be set/cleared
750 * to configure the pins for SCC2 use.
751 */
752#define PROFF_ENET PROFF_SCC2
753#define CPM_CR_ENET CPM_CR_CH_SCC2
754#define SCC_ENET 1
755#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
756#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
757#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
758#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
759
760#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
761
762#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
763#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
764
765/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
766 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
767 */
768#define SICR_ENET_MASK ((uint)0x0000ff00)
769#define SICR_ENET_CLKRT ((uint)0x00003E00)
770#endif /* CONFIG_LWMON */
771
Heiko Schocherd0449542009-03-12 07:37:28 +0100772/*** KM8XX *********************************************************/
Heiko Schocher381e4e62008-01-11 01:12:06 +0100773
Heiko Schocherd0449542009-03-12 07:37:28 +0100774/* The KM8XX Service Module uses SCC3 for Ethernet */
Heiko Schocher381e4e62008-01-11 01:12:06 +0100775
Heiko Schocherd0449542009-03-12 07:37:28 +0100776#ifdef CONFIG_KM8XX
Heiko Schocher381e4e62008-01-11 01:12:06 +0100777#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
778#define CPM_CR_ENET CPM_CR_CH_SCC3
779#define SCC_ENET 2
780#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
781#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
782#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
783#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
784
785#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
786
787#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
788#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
789
790/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
791 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
792 */
793#define SICR_ENET_MASK ((uint)0x00FF0000)
794#define SICR_ENET_CLKRT ((uint)0x00250000)
Heiko Schocherd0449542009-03-12 07:37:28 +0100795#endif /* CONFIG_KM8XX */
Heiko Schocher381e4e62008-01-11 01:12:06 +0100796
797
wdenkfe8c2802002-11-03 00:38:21 +0000798/*** MHPC ********************************************************/
799
800#if defined(CONFIG_MHPC)
801/* This ENET stuff is for the MHPC with ethernet on SCC2.
802 * Note TENA is on Port B.
803 */
804#define PROFF_ENET PROFF_SCC2
805#define CPM_CR_ENET CPM_CR_CH_SCC2
806#define SCC_ENET 1
807#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
808#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
809#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
810#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
811#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
812#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
813#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
814
815#define SICR_ENET_MASK ((uint)0x0000ff00)
816#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
817#endif /* CONFIG_MHPC */
818
wdenk608c9142003-01-13 23:54:46 +0000819/*** NETVIA *******************************************************/
820
wdenkdc7c9a12003-03-26 06:55:25 +0000821/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
822#if ( defined CONFIG_SVM_SC8xx )
823# ifndef CONFIG_FEC_ENET
824
825#define PROFF_ENET PROFF_SCC2
826#define CPM_CR_ENET CPM_CR_CH_SCC2
827#define SCC_ENET 1
828
829 /* Bits in parallel I/O port registers that have to be set/cleared
830 * * * * to configure the pins for SCC2 use.
831 * * * */
832#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
833#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
834#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
835#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
836
837#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
838
839#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
840#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
841/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
842 * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
843 * * * */
844#define SICR_ENET_MASK ((uint)0x0000ff00)
845#define SICR_ENET_CLKRT ((uint)0x00003700)
846
847# else /* Use FEC for Fast Ethernet */
848
849#undef SCC_ENET
850#define FEC_ENET
851
852#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
853#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
854#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
855#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
856#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
857#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
858#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
859#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
860#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
861#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
862#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
863#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
864#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
865
866#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
867
868# endif /* CONFIG_FEC_ENET */
869#endif /* CONFIG_SVM_SC8xx */
wdenk8bde7f72003-06-27 21:31:46 +0000870
871
wdenk608c9142003-01-13 23:54:46 +0000872#if defined(CONFIG_NETVIA)
873/* Bits in parallel I/O port registers that have to be set/cleared
874 * to configure the pins for SCC2 use.
875 */
876#define PROFF_ENET PROFF_SCC2
877#define CPM_CR_ENET CPM_CR_CH_SCC2
878#define SCC_ENET 1
879#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
880#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
881#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
882#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
883
wdenk993cad92003-06-26 22:04:09 +0000884#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
885# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
886#elif CONFIG_NETVIA_VERSION >= 2
887# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
888#endif
889
wdenk608c9142003-01-13 23:54:46 +0000890#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
891
892#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
893#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
894
895/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
896 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
897 */
898#define SICR_ENET_MASK ((uint)0x0000ff00)
899#define SICR_ENET_CLKRT ((uint)0x00002f00)
900
901#endif /* CONFIG_NETVIA */
902
wdenk3bbc8992003-12-07 22:27:15 +0000903/*** QS850/QS823 ***************************************************/
904
905#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
906#undef FEC_ENET /* Don't use FEC for EThernet */
907
908#define PROFF_ENET PROFF_SCC2
909#define CPM_CR_ENET CPM_CR_CH_SCC2
910#define SCC_ENET 1
911
912#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
913#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
914#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
915#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
916#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
917#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
918#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
919#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
920#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
921#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
922
923/* SCC2 TXCLK from CLK2
924 * SCC2 RXCLK from CLK4
925 * SCC2 Connected to NMSI */
926#define SICR_ENET_MASK ((uint)0x00007F00)
927#define SICR_ENET_CLKRT ((uint)0x00003D00)
928
929#endif /* CONFIG_QS850/QS823 */
930
931/*** QS860T ***************************************************/
932
933#ifdef CONFIG_QS860T
934#ifdef CONFIG_FEC_ENET
935#define FEC_ENET /* use FEC for EThernet */
936#endif /* CONFIG_FEC_ETHERNET */
937
938/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
939#define PROFF_ENET PROFF_SCC1
940#define CPM_CR_ENET CPM_CR_CH_SCC1
941#define SCC_ENET 0
942
943#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
944#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
945#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
946#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
947#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
948#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
949#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
950
951#define SICR_ENET_MASK ((uint)0x000000ff)
952/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
953#define SICR_ENET_CLKRT ((uint)0x0000003D)
954
955#endif /* CONFIG_QS860T */
956
wdenkfe8c2802002-11-03 00:38:21 +0000957/*** RPXLITE ********************************************************/
958
959#ifdef CONFIG_RPXLITE
960/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
961 * this may be unique to the RPX-Lite configuration.
962 * Note TENA is on Port B.
963 */
964#define PROFF_ENET PROFF_SCC2
965#define CPM_CR_ENET CPM_CR_CH_SCC2
966#define SCC_ENET 1
967#define PA_ENET_RXD ((ushort)0x0004)
968#define PA_ENET_TXD ((ushort)0x0008)
969#define PA_ENET_TCLK ((ushort)0x0200)
970#define PA_ENET_RCLK ((ushort)0x0800)
wdenk73a8b272003-06-05 19:27:42 +0000971#if defined(CONFIG_RMU)
972#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
973#else
wdenkfe8c2802002-11-03 00:38:21 +0000974#define PB_ENET_TENA ((uint)0x00002000)
wdenk73a8b272003-06-05 19:27:42 +0000975#endif
wdenkfe8c2802002-11-03 00:38:21 +0000976#define PC_ENET_CLSN ((ushort)0x0040)
977#define PC_ENET_RENA ((ushort)0x0080)
978
979#define SICR_ENET_MASK ((uint)0x0000ff00)
980#define SICR_ENET_CLKRT ((uint)0x00003d00)
981#endif /* CONFIG_RPXLITE */
982
983/*** SM850 *********************************************************/
984
985/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
986
987#ifdef CONFIG_SM850
988#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
989#define CPM_CR_ENET CPM_CR_CH_SCC3
990#define SCC_ENET 2
991#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
992#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
993#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
994#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
995
996#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
997#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
998
999#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
1000#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
1001
1002/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1003 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1004 */
1005#define SICR_ENET_MASK ((uint)0x00FF0000)
1006#define SICR_ENET_CLKRT ((uint)0x00260000)
1007#endif /* CONFIG_SM850 */
1008
1009/*** SPD823TS ******************************************************/
1010
1011#ifdef CONFIG_SPD823TS
1012/* Bits in parallel I/O port registers that have to be set/cleared
1013 * to configure the pins for SCC2 use.
1014 */
1015#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
1016#define CPM_CR_ENET CPM_CR_CH_SCC2
1017#define SCC_ENET 1
1018#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
1019#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
1020#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1021#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1022#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1023#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1024
1025#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1026
1027#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1028#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1029#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
1030
1031/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1032 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1033 */
1034#define SICR_ENET_MASK ((uint)0x0000ff00)
1035#define SICR_ENET_CLKRT ((uint)0x00002E00)
1036#endif /* CONFIG_SPD823TS */
1037
1038/*** SXNI855T ******************************************************/
1039
1040#if defined(CONFIG_SXNI855T)
1041
1042#ifdef CONFIG_FEC_ENET
1043#define FEC_ENET /* use FEC for Ethernet */
1044#endif /* CONFIG_FEC_ETHERNET */
1045
1046#endif /* CONFIG_SXNI855T */
1047
Wolfgang Denk1b0757e2012-10-24 02:36:15 +00001048/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
wdenkfe8c2802002-11-03 00:38:21 +00001049
1050#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
wdenk71f95112003-06-15 22:40:42 +00001051 defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
Wolfgang Denk1b0757e2012-10-24 02:36:15 +00001052 defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
1053 defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
1054 defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
1055 defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001056
wdenkfe8c2802002-11-03 00:38:21 +00001057/* Bits in parallel I/O port registers that have to be set/cleared
1058 * to configure the pins for SCC2 use.
1059 */
1060#define PROFF_ENET PROFF_SCC2
1061#define CPM_CR_ENET CPM_CR_CH_SCC2
Wolfgang Denk2b4f7782008-01-15 17:21:28 +01001062#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */
wdenkfe8c2802002-11-03 00:38:21 +00001063#define SCC_ENET 1
Wolfgang Denk2b4f7782008-01-15 17:21:28 +01001064#endif
wdenkfe8c2802002-11-03 00:38:21 +00001065#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1066#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1067#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1068#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1069
1070#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1071
1072#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1073#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1074#if defined(CONFIG_R360MPI)
1075#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1076#endif /* CONFIG_R360MPI */
1077
1078/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1079 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1080 */
1081#define SICR_ENET_MASK ((uint)0x0000ff00)
1082#define SICR_ENET_CLKRT ((uint)0x00002600)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001083
1084# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1085#define FEC_ENET
1086# endif /* CONFIG_FEC_ENET */
1087
wdenk71f95112003-06-15 22:40:42 +00001088#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
wdenkfe8c2802002-11-03 00:38:21 +00001089
wdenkd4ca31c2004-01-02 14:00:00 +00001090/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
wdenkfe8c2802002-11-03 00:38:21 +00001091
wdenk71f95112003-06-15 22:40:42 +00001092#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
1093 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
wdenkd4ca31c2004-01-02 14:00:00 +00001094 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
1095 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
wdenkfe8c2802002-11-03 00:38:21 +00001096
1097# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
1098
1099/* Bits in parallel I/O port registers that have to be set/cleared
1100 * to configure the pins for SCC1 use.
1101 */
1102#define PROFF_ENET PROFF_SCC1
1103#define CPM_CR_ENET CPM_CR_CH_SCC1
1104#define SCC_ENET 0
1105#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
1106#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
1107#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1108#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1109
1110#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
1111#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
1112#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
1113
1114/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1115 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1116 */
1117#define SICR_ENET_MASK ((uint)0x000000ff)
1118#define SICR_ENET_CLKRT ((uint)0x00000026)
1119
1120# endif /* CONFIG_SCC1_ENET */
1121
1122# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1123
1124#define FEC_ENET
1125
1126#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
1127#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
1128#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
1129#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1130#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1131#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1132#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1133#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1134#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1135#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1136#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1137#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1138#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1139
1140#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1141
1142# endif /* CONFIG_FEC_ENET */
wdenk71f95112003-06-15 22:40:42 +00001143#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
wdenkfe8c2802002-11-03 00:38:21 +00001144
wdenk608c9142003-01-13 23:54:46 +00001145/*** V37 **********************************************************/
1146
1147#ifdef CONFIG_V37
1148/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
1149 * this may be unique to the Marel V37 configuration.
1150 * Note TENA is on Port B.
wdenkfe8c2802002-11-03 00:38:21 +00001151 */
1152#define PROFF_ENET PROFF_SCC2
1153#define CPM_CR_ENET CPM_CR_CH_SCC2
1154#define SCC_ENET 1
wdenk608c9142003-01-13 23:54:46 +00001155#define PA_ENET_RXD ((ushort)0x0004)
1156#define PA_ENET_TXD ((ushort)0x0008)
1157#define PA_ENET_TCLK ((ushort)0x0400)
1158#define PA_ENET_RCLK ((ushort)0x0200)
1159#define PB_ENET_TENA ((uint)0x00002000)
1160#define PC_ENET_CLSN ((ushort)0x0040)
1161#define PC_ENET_RENA ((ushort)0x0080)
wdenkfe8c2802002-11-03 00:38:21 +00001162
wdenkfe8c2802002-11-03 00:38:21 +00001163#define SICR_ENET_MASK ((uint)0x0000ff00)
wdenk608c9142003-01-13 23:54:46 +00001164#define SICR_ENET_CLKRT ((uint)0x00002e00)
1165#endif /* CONFIG_V37 */
wdenkfe8c2802002-11-03 00:38:21 +00001166
wdenk3bbc8992003-12-07 22:27:15 +00001167
wdenkfe8c2802002-11-03 00:38:21 +00001168/*********************************************************************/
1169
1170/* SCC Event register as used by Ethernet.
1171*/
1172#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
1173#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
1174#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
1175#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
1176#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
1177#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
1178
1179/* SCC Mode Register (PSMR) as used by Ethernet.
1180*/
1181#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
1182#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
1183#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
1184#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
1185#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
1186#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
1187#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
1188#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
1189#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
1190#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
1191#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
1192#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
1193#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
1194
1195/* Buffer descriptor control/status used by Ethernet receive.
1196*/
1197#define BD_ENET_RX_EMPTY ((ushort)0x8000)
1198#define BD_ENET_RX_WRAP ((ushort)0x2000)
1199#define BD_ENET_RX_INTR ((ushort)0x1000)
1200#define BD_ENET_RX_LAST ((ushort)0x0800)
1201#define BD_ENET_RX_FIRST ((ushort)0x0400)
1202#define BD_ENET_RX_MISS ((ushort)0x0100)
1203#define BD_ENET_RX_LG ((ushort)0x0020)
1204#define BD_ENET_RX_NO ((ushort)0x0010)
1205#define BD_ENET_RX_SH ((ushort)0x0008)
1206#define BD_ENET_RX_CR ((ushort)0x0004)
1207#define BD_ENET_RX_OV ((ushort)0x0002)
1208#define BD_ENET_RX_CL ((ushort)0x0001)
1209#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
1210
1211/* Buffer descriptor control/status used by Ethernet transmit.
1212*/
1213#define BD_ENET_TX_READY ((ushort)0x8000)
1214#define BD_ENET_TX_PAD ((ushort)0x4000)
1215#define BD_ENET_TX_WRAP ((ushort)0x2000)
1216#define BD_ENET_TX_INTR ((ushort)0x1000)
1217#define BD_ENET_TX_LAST ((ushort)0x0800)
1218#define BD_ENET_TX_TC ((ushort)0x0400)
1219#define BD_ENET_TX_DEF ((ushort)0x0200)
1220#define BD_ENET_TX_HB ((ushort)0x0100)
1221#define BD_ENET_TX_LC ((ushort)0x0080)
1222#define BD_ENET_TX_RL ((ushort)0x0040)
1223#define BD_ENET_TX_RCMASK ((ushort)0x003c)
1224#define BD_ENET_TX_UN ((ushort)0x0002)
1225#define BD_ENET_TX_CSL ((ushort)0x0001)
1226#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
1227
1228/* SCC as UART
1229*/
1230typedef struct scc_uart {
1231 sccp_t scc_genscc;
1232 uint scc_res1; /* Reserved */
1233 uint scc_res2; /* Reserved */
1234 ushort scc_maxidl; /* Maximum idle chars */
1235 ushort scc_idlc; /* temp idle counter */
1236 ushort scc_brkcr; /* Break count register */
1237 ushort scc_parec; /* receive parity error counter */
1238 ushort scc_frmec; /* receive framing error counter */
1239 ushort scc_nosec; /* receive noise counter */
1240 ushort scc_brkec; /* receive break condition counter */
1241 ushort scc_brkln; /* last received break length */
1242 ushort scc_uaddr1; /* UART address character 1 */
1243 ushort scc_uaddr2; /* UART address character 2 */
1244 ushort scc_rtemp; /* Temp storage */
1245 ushort scc_toseq; /* Transmit out of sequence char */
1246 ushort scc_char1; /* control character 1 */
1247 ushort scc_char2; /* control character 2 */
1248 ushort scc_char3; /* control character 3 */
1249 ushort scc_char4; /* control character 4 */
1250 ushort scc_char5; /* control character 5 */
1251 ushort scc_char6; /* control character 6 */
1252 ushort scc_char7; /* control character 7 */
1253 ushort scc_char8; /* control character 8 */
1254 ushort scc_rccm; /* receive control character mask */
1255 ushort scc_rccr; /* receive control character register */
1256 ushort scc_rlbc; /* receive last break character */
1257} scc_uart_t;
1258
1259/* SCC Event and Mask registers when it is used as a UART.
1260*/
1261#define UART_SCCM_GLR ((ushort)0x1000)
1262#define UART_SCCM_GLT ((ushort)0x0800)
1263#define UART_SCCM_AB ((ushort)0x0200)
1264#define UART_SCCM_IDL ((ushort)0x0100)
1265#define UART_SCCM_GRA ((ushort)0x0080)
1266#define UART_SCCM_BRKE ((ushort)0x0040)
1267#define UART_SCCM_BRKS ((ushort)0x0020)
1268#define UART_SCCM_CCR ((ushort)0x0008)
1269#define UART_SCCM_BSY ((ushort)0x0004)
1270#define UART_SCCM_TX ((ushort)0x0002)
1271#define UART_SCCM_RX ((ushort)0x0001)
1272
1273/* The SCC PSMR when used as a UART.
1274*/
1275#define SCU_PSMR_FLC ((ushort)0x8000)
1276#define SCU_PSMR_SL ((ushort)0x4000)
1277#define SCU_PSMR_CL ((ushort)0x3000)
1278#define SCU_PSMR_UM ((ushort)0x0c00)
1279#define SCU_PSMR_FRZ ((ushort)0x0200)
1280#define SCU_PSMR_RZS ((ushort)0x0100)
1281#define SCU_PSMR_SYN ((ushort)0x0080)
1282#define SCU_PSMR_DRT ((ushort)0x0040)
1283#define SCU_PSMR_PEN ((ushort)0x0010)
1284#define SCU_PSMR_RPM ((ushort)0x000c)
1285#define SCU_PSMR_REVP ((ushort)0x0008)
1286#define SCU_PSMR_TPM ((ushort)0x0003)
1287#define SCU_PSMR_TEVP ((ushort)0x0003)
1288
1289/* CPM Transparent mode SCC.
1290 */
1291typedef struct scc_trans {
1292 sccp_t st_genscc;
1293 uint st_cpres; /* Preset CRC */
1294 uint st_cmask; /* Constant mask for CRC */
1295} scc_trans_t;
1296
1297#define BD_SCC_TX_LAST ((ushort)0x0800)
1298
1299/* IIC parameter RAM.
1300*/
1301typedef struct iic {
1302 ushort iic_rbase; /* Rx Buffer descriptor base address */
1303 ushort iic_tbase; /* Tx Buffer descriptor base address */
1304 u_char iic_rfcr; /* Rx function code */
1305 u_char iic_tfcr; /* Tx function code */
1306 ushort iic_mrblr; /* Max receive buffer length */
1307 uint iic_rstate; /* Internal */
1308 uint iic_rdp; /* Internal */
1309 ushort iic_rbptr; /* Internal */
1310 ushort iic_rbc; /* Internal */
1311 uint iic_rxtmp; /* Internal */
1312 uint iic_tstate; /* Internal */
1313 uint iic_tdp; /* Internal */
1314 ushort iic_tbptr; /* Internal */
1315 ushort iic_tbc; /* Internal */
1316 uint iic_txtmp; /* Internal */
1317 uint iic_res; /* reserved */
1318 ushort iic_rpbase; /* Relocation pointer */
1319 ushort iic_res2; /* reserved */
1320} iic_t;
1321
1322/* SPI parameter RAM.
1323*/
1324typedef struct spi {
1325 ushort spi_rbase; /* Rx Buffer descriptor base address */
1326 ushort spi_tbase; /* Tx Buffer descriptor base address */
1327 u_char spi_rfcr; /* Rx function code */
1328 u_char spi_tfcr; /* Tx function code */
1329 ushort spi_mrblr; /* Max receive buffer length */
1330 uint spi_rstate; /* Internal */
1331 uint spi_rdp; /* Internal */
1332 ushort spi_rbptr; /* Internal */
1333 ushort spi_rbc; /* Internal */
1334 uint spi_rxtmp; /* Internal */
1335 uint spi_tstate; /* Internal */
1336 uint spi_tdp; /* Internal */
1337 ushort spi_tbptr; /* Internal */
1338 ushort spi_tbc; /* Internal */
1339 uint spi_txtmp; /* Internal */
1340 uint spi_res;
1341 ushort spi_rpbase; /* Relocation pointer */
1342 ushort spi_res2;
1343} spi_t;
1344
1345/* SPI Mode register.
1346*/
1347#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
1348#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
1349#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
1350#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
1351#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
1352#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
1353#define SPMODE_EN ((ushort)0x0100) /* Enable */
1354#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
1355#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
1356
1357#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
1358#define SPMODE_PM(x) ((x) &0xF)
1359
1360/* HDLC parameter RAM.
1361*/
1362
1363typedef struct hdlc_pram_s {
1364 /*
1365 * SCC parameter RAM
1366 */
1367 ushort rbase; /* Rx Buffer descriptor base address */
1368 ushort tbase; /* Tx Buffer descriptor base address */
1369 uchar rfcr; /* Rx function code */
1370 uchar tfcr; /* Tx function code */
1371 ushort mrblr; /* Rx buffer length */
1372 ulong rstate; /* Rx internal state */
1373 ulong rptr; /* Rx internal data pointer */
1374 ushort rbptr; /* rb BD Pointer */
1375 ushort rcount; /* Rx internal byte count */
1376 ulong rtemp; /* Rx temp */
1377 ulong tstate; /* Tx internal state */
1378 ulong tptr; /* Tx internal data pointer */
1379 ushort tbptr; /* Tx BD pointer */
1380 ushort tcount; /* Tx byte count */
1381 ulong ttemp; /* Tx temp */
1382 ulong rcrc; /* temp receive CRC */
1383 ulong tcrc; /* temp transmit CRC */
1384 /*
1385 * HDLC specific parameter RAM
1386 */
1387 uchar res[4]; /* reserved */
1388 ulong c_mask; /* CRC constant */
1389 ulong c_pres; /* CRC preset */
1390 ushort disfc; /* discarded frame counter */
1391 ushort crcec; /* CRC error counter */
1392 ushort abtsc; /* abort sequence counter */
1393 ushort nmarc; /* nonmatching address rx cnt */
1394 ushort retrc; /* frame retransmission cnt */
1395 ushort mflr; /* maximum frame length reg */
1396 ushort max_cnt; /* maximum length counter */
1397 ushort rfthr; /* received frames threshold */
1398 ushort rfcnt; /* received frames count */
1399 ushort hmask; /* user defined frm addr mask */
1400 ushort haddr1; /* user defined frm address 1 */
1401 ushort haddr2; /* user defined frm address 2 */
1402 ushort haddr3; /* user defined frm address 3 */
1403 ushort haddr4; /* user defined frm address 4 */
1404 ushort tmp; /* temp */
1405 ushort tmp_mb; /* temp */
1406} hdlc_pram_t;
1407
1408/* CPM interrupts. There are nearly 32 interrupts generated by CPM
1409 * channels or devices. All of these are presented to the PPC core
1410 * as a single interrupt. The CPM interrupt handler dispatches its
1411 * own handlers, in a similar fashion to the PPC core handler. We
1412 * use the table as defined in the manuals (i.e. no special high
1413 * priority and SCC1 == SCCa, etc...).
1414 */
1415#define CPMVEC_NR 32
wdenk7c7a23b2002-12-07 00:20:59 +00001416#define CPMVEC_OFFSET 0x00010000
1417#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
1418#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
1419#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
1420#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
1421#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
1422#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
1423#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
1424#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
1425#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
1426#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
1427#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
1428#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
1429#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
1430#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
1431#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
1432#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
1433#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
1434#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
1435#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
1436#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
1437#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
1438#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
1439#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
1440#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
1441#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
1442#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
1443#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
1444#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
1445#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
wdenkfe8c2802002-11-03 00:38:21 +00001446
1447extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1448
1449/* CPM interrupt configuration vector.
1450*/
1451#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
1452#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
1453#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
1454#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
1455#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
1456#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
1457#define CICR_IEN ((uint)0x00000080) /* Int. enable */
1458#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
1459#endif /* __CPM_8XX__ */