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Vladimir Zapolskiy463ec1c2012-04-19 04:33:10 +00001/*
2 * Embest/Timll DevKit3250 board support
3 *
Vladimir Zapolskiy768ddee2015-07-18 01:47:10 +03004 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy463ec1c2012-04-19 04:33:10 +00005 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Vladimir Zapolskiy463ec1c2012-04-19 04:33:10 +00007 */
8
9#include <common.h>
10#include <asm/arch/sys_proto.h>
Vladimir Zapolskiy768ddee2015-07-18 01:47:10 +030011#include <asm/arch/clk.h>
Vladimir Zapolskiy463ec1c2012-04-19 04:33:10 +000012#include <asm/arch/cpu.h>
13#include <asm/arch/emc.h>
Vladimir Zapolskiy768ddee2015-07-18 01:47:10 +030014#include <asm/arch/wdt.h>
15#include <asm/io.h>
Vladimir Zapolskiy463ec1c2012-04-19 04:33:10 +000016
17DECLARE_GLOBAL_DATA_PTR;
18
19static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
Vladimir Zapolskiy768ddee2015-07-18 01:47:10 +030020static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
21static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
22
23void reset_periph(void)
24{
25 /* This function resets peripherals by triggering RESOUT_N */
26 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
27 writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
28 udelay(300);
29
30 writel(0, &wdt->mctrl);
31 clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
32
33 /* Such a long delay is needed to initialize SMSC phy */
34 udelay(10000);
35}
Vladimir Zapolskiy463ec1c2012-04-19 04:33:10 +000036
37int board_early_init_f(void)
38{
39 lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
Vladimir Zapolskiy768ddee2015-07-18 01:47:10 +030040 lpc32xx_i2c_init(1);
41 lpc32xx_i2c_init(2);
42 lpc32xx_ssp_init();
43 lpc32xx_mac_init();
44
45 /*
46 * nWP may be controlled by GPO19, but unpopulated by default R23
47 * makes no sense to configure this GPIO level, nWP is always high
48 */
49 lpc32xx_slc_nand_init();
Vladimir Zapolskiy463ec1c2012-04-19 04:33:10 +000050
51 return 0;
52}
53
54int board_init(void)
55{
56 /* adress of boot parameters */
57 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
58
59#ifdef CONFIG_SYS_FLASH_CFI
60 /* Use 16-bit memory interface for NOR Flash */
61 emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
62
63 /* Change the NOR timings to optimum value to get maximum bandwidth */
64 emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
Vladimir Zapolskiyf0aa26f2015-10-04 23:18:24 +010065 emc->stat[0].waitoen = EMC_STAT_WAITOEN(0);
Vladimir Zapolskiy463ec1c2012-04-19 04:33:10 +000066 emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
67 emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
68 emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
69 emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
70#endif
71
72 return 0;
73}
74
75int dram_init(void)
76{
77 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
78 CONFIG_SYS_SDRAM_SIZE);
79
80 return 0;
81}