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Dirk Eibach2da0fc02011-01-21 09:31:21 +01001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach2da0fc02011-01-21 09:31:21 +01006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
12#define CONFIG_4xx 1 /* member of PPC4xx family */
13#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
14
15#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
16
17/*
18 * Include common defines/options for all AMCC eval boards
19 */
20#define CONFIG_HOSTNAME dlvsion-10g
Dirk Eibach3e24dd22013-08-09 10:52:54 +020021#define CONFIG_IDENT_STRING " dlvision-10g 0.05"
Dirk Eibach2da0fc02011-01-21 09:31:21 +010022#include "amcc-common.h"
23
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000024#define CONFIG_BOARD_EARLY_INIT_F
25#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibachb19bf832012-04-26 03:54:23 +000026#define CONFIG_MISC_INIT_R
Dirk Eibach2da0fc02011-01-21 09:31:21 +010027#define CONFIG_LAST_STAGE_INIT
28
29#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
30
Dirk Eibach6cfa9ee2011-04-06 13:53:50 +020031#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
32#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
33#define CONFIG_AUTOBOOT_STOP_STR " "
34
Dirk Eibach2da0fc02011-01-21 09:31:21 +010035/*
36 * Configure PLL
37 */
38#define PLLMR0_DEFAULT PLLMR0_266_133_66
39#define PLLMR1_DEFAULT PLLMR1_266_133_66
40
41/* new uImage format support */
42#define CONFIG_FIT
43#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
44
45#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
46
47/*
48 * Default environment variables
49 */
50#define CONFIG_EXTRA_ENV_SETTINGS \
51 CONFIG_AMCC_DEF_ENV \
52 CONFIG_AMCC_DEF_ENV_POWERPC \
53 CONFIG_AMCC_DEF_ENV_NOR_UPD \
54 "kernel_addr=fc000000\0" \
55 "fdt_addr=fc1e0000\0" \
56 "ramdisk_addr=fc200000\0" \
57 ""
58
59#define CONFIG_PHY_ADDR 4 /* PHY address */
60#define CONFIG_HAS_ETH0
61#define CONFIG_HAS_ETH1
62#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
63#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
64
65/*
66 * Commands additional to the ones defined in amcc-common.h
67 */
68#define CONFIG_CMD_CACHE
Dirk Eibachb19bf832012-04-26 03:54:23 +000069#define CONFIG_CMD_DTT
Dirk Eibach2da0fc02011-01-21 09:31:21 +010070#undef CONFIG_CMD_EEPROM
71
72/*
73 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
74 */
75#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
76
77/* SDRAM timings used in datasheet */
78#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
79#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
80#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
81#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
82#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
83
84/*
85 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
86 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
87 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
88 * The Linux BASE_BAUD define should match this configuration.
89 * baseBaud = cpuClock/(uartDivisor*16)
90 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
91 * set Linux BASE_BAUD to 403200.
92 */
93#define CONFIG_CONS_INDEX 1 /* Use UART0 */
94#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
95#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
96#define CONFIG_SYS_BASE_BAUD 691200
97
98/*
99 * I2C stuff
100 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000101#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100102
103/* Temp sensor/hwmon/dtt */
104#define CONFIG_DTT_LM63 1 /* National LM63 */
Dirk Eibach2ade7be2012-04-26 03:54:24 +0000105#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100106#define CONFIG_DTT_PWM_LOOKUPTABLE \
Dirk Eibach97ca7b32011-10-04 11:13:53 +0200107 { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
108 { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100109#define CONFIG_DTT_TACH_LIMIT 0xa10
110
111/* EBC peripherals */
112
113#define CONFIG_SYS_FLASH_BASE 0xFC000000
114#define CONFIG_SYS_FPGA0_BASE 0x7f100000
115#define CONFIG_SYS_FPGA1_BASE 0x7f200000
116#define CONFIG_SYS_LATCH_BASE 0x7f300000
117
118#define CONFIG_SYS_FPGA_BASE(k) \
119 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
120
121#define CONFIG_SYS_FPGA_DONE(k) \
122 (k ? 0x2000 : 0x1000)
123
124#define CONFIG_SYS_FPGA_COUNT 2
125
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200126#define CONFIG_SYS_FPGA_PTR { \
127 (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
128 (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
129
130#define CONFIG_SYS_FPGA_COMMON
131
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100132#define CONFIG_SYS_LATCH0_RESET 0xffff
133#define CONFIG_SYS_LATCH0_BOOT 0xffff
Dirk Eibach3e24dd22013-08-09 10:52:54 +0200134#define CONFIG_SYS_LATCH1_RESET 0xffbf
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100135#define CONFIG_SYS_LATCH1_BOOT 0xffff
136
Dirk Eibach5cb41002011-04-06 13:53:46 +0200137#define CONFIG_SYS_FPGA_NO_RFL_HI
138
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100139/*
140 * FLASH organization
141 */
142#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
143#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
144
145#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
146
147#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
148#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
149
150#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
151#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
152
153#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100154
155#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
156#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
157
158#ifdef CONFIG_ENV_IS_IN_FLASH
159#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
160#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
161#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
162
163/* Address and size of Redundant Environment Sector */
164#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
165#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
166#endif
167
168/*
169 * PPC405 GPIO Configuration
170 */
171#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
172{ \
173/* GPIO Core 0 */ \
174{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
175{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
176{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
177{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
178{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
179{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
180{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
181{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
182{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
183{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
184{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
185{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
186{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
187{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
188{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
189{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
190{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
191{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
192{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
193{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
194{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
195{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
196{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
197{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
198{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
199{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
200{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
201{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
202{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
203{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
204{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
205{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
206} \
207}
208
209/*
210 * Definitions for initial stack pointer and data area (in data cache)
211 */
212/* use on chip memory (OCM) for temperary stack until sdram is tested */
213#define CONFIG_SYS_TEMP_STACK_OCM 1
214
215/* On Chip Memory location */
216#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
217#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
218#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
219#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
220
221#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
222#define CONFIG_SYS_GBL_DATA_OFFSET \
223 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
224#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
225
226/*
227 * External Bus Controller (EBC) Setup
228 */
229
230/* Memory Bank 0 (NOR-flash) */
231#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
232 EBC_BXAP_FWT_ENCODE(8) | \
233 EBC_BXAP_BWT_ENCODE(7) | \
234 EBC_BXAP_BCE_DISABLE | \
235 EBC_BXAP_BCT_2TRANS | \
236 EBC_BXAP_CSN_ENCODE(0) | \
237 EBC_BXAP_OEN_ENCODE(2) | \
238 EBC_BXAP_WBN_ENCODE(2) | \
239 EBC_BXAP_WBF_ENCODE(2) | \
240 EBC_BXAP_TH_ENCODE(4) | \
241 EBC_BXAP_RE_DISABLED | \
242 EBC_BXAP_SOR_NONDELAYED | \
243 EBC_BXAP_BEM_WRITEONLY | \
244 EBC_BXAP_PEN_DISABLED)
245#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
246 EBC_BXCR_BS_64MB | \
247 EBC_BXCR_BU_RW | \
248 EBC_BXCR_BW_16BIT)
249
250/* Memory Bank 1 (FPGA0) */
251#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
252 EBC_BXAP_TWT_ENCODE(5) | \
253 EBC_BXAP_BCE_DISABLE | \
254 EBC_BXAP_BCT_2TRANS | \
255 EBC_BXAP_CSN_ENCODE(0) | \
256 EBC_BXAP_OEN_ENCODE(2) | \
257 EBC_BXAP_WBN_ENCODE(1) | \
258 EBC_BXAP_WBF_ENCODE(1) | \
259 EBC_BXAP_TH_ENCODE(0) | \
260 EBC_BXAP_RE_DISABLED | \
261 EBC_BXAP_SOR_NONDELAYED | \
262 EBC_BXAP_BEM_WRITEONLY | \
263 EBC_BXAP_PEN_DISABLED)
264#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
265 EBC_BXCR_BS_1MB | \
266 EBC_BXCR_BU_RW | \
267 EBC_BXCR_BW_16BIT)
268
269/* Memory Bank 2 (FPGA1) */
270#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
271 EBC_BXAP_TWT_ENCODE(6) | \
272 EBC_BXAP_BCE_DISABLE | \
273 EBC_BXAP_BCT_2TRANS | \
274 EBC_BXAP_CSN_ENCODE(0) | \
275 EBC_BXAP_OEN_ENCODE(2) | \
276 EBC_BXAP_WBN_ENCODE(1) | \
277 EBC_BXAP_WBF_ENCODE(1) | \
278 EBC_BXAP_TH_ENCODE(0) | \
279 EBC_BXAP_RE_DISABLED | \
280 EBC_BXAP_SOR_NONDELAYED | \
281 EBC_BXAP_BEM_WRITEONLY | \
282 EBC_BXAP_PEN_DISABLED)
283#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
284 EBC_BXCR_BS_1MB | \
285 EBC_BXCR_BU_RW | \
286 EBC_BXCR_BW_16BIT)
287
288/* Memory Bank 3 (Latches) */
289#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
290 EBC_BXAP_FWT_ENCODE(8) | \
291 EBC_BXAP_BWT_ENCODE(4) | \
292 EBC_BXAP_BCE_DISABLE | \
293 EBC_BXAP_BCT_2TRANS | \
294 EBC_BXAP_CSN_ENCODE(0) | \
295 EBC_BXAP_OEN_ENCODE(1) | \
296 EBC_BXAP_WBN_ENCODE(1) | \
297 EBC_BXAP_WBF_ENCODE(1) | \
298 EBC_BXAP_TH_ENCODE(2) | \
299 EBC_BXAP_RE_DISABLED | \
300 EBC_BXAP_SOR_NONDELAYED | \
301 EBC_BXAP_BEM_WRITEONLY | \
302 EBC_BXAP_PEN_DISABLED)
303#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
304 EBC_BXCR_BS_1MB | \
305 EBC_BXCR_BU_RW | \
306 EBC_BXCR_BW_16BIT)
307
308/*
309 * OSD Setup
310 */
311#define CONFIG_SYS_ICS8N3QV01
Dirk Eibach7749c842011-04-06 13:53:48 +0200312#define CONFIG_SYS_MPC92469AC
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100313#define CONFIG_SYS_SIL1178
314#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
315
316#endif /* __CONFIG_H */