blob: 4ac4612c81ea48073a1e67280f06a57e848c01b8 [file] [log] [blame]
Simon Glassbfe8fa22021-02-06 14:23:35 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Google LLC
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <log.h>
9#include <tpm_api.h>
10#include <tpm-v1.h>
11#include <tpm-v2.h>
12#include <tpm_api.h>
13
Simon Glassbfe8fa22021-02-06 14:23:35 -070014u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode)
15{
Simon Glass5e593782022-07-22 21:32:02 +053016 if (tpm_is_v1(dev)) {
Simon Glassbfe8fa22021-02-06 14:23:35 -070017 return tpm1_startup(dev, mode);
Simon Glass5e593782022-07-22 21:32:02 +053018 } else if (tpm_is_v2(dev)) {
Simon Glassb8eb9212021-02-06 14:23:37 -070019 enum tpm2_startup_types type;
20
21 switch (mode) {
22 case TPM_ST_CLEAR:
23 type = TPM2_SU_CLEAR;
24 break;
25 case TPM_ST_STATE:
26 type = TPM2_SU_STATE;
27 break;
28 default:
29 case TPM_ST_DEACTIVATED:
30 return -EINVAL;
31 }
32 return tpm2_startup(dev, type);
33 } else {
Simon Glassbfe8fa22021-02-06 14:23:35 -070034 return -ENOSYS;
Simon Glassb8eb9212021-02-06 14:23:37 -070035 }
Simon Glassbfe8fa22021-02-06 14:23:35 -070036}
37
38u32 tpm_resume(struct udevice *dev)
39{
Simon Glass5e593782022-07-22 21:32:02 +053040 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -070041 return tpm1_startup(dev, TPM_ST_STATE);
Simon Glass5e593782022-07-22 21:32:02 +053042 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -070043 return tpm2_startup(dev, TPM2_SU_STATE);
Simon Glassbfe8fa22021-02-06 14:23:35 -070044 else
45 return -ENOSYS;
46}
47
48u32 tpm_self_test_full(struct udevice *dev)
49{
Simon Glass5e593782022-07-22 21:32:02 +053050 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -070051 return tpm1_self_test_full(dev);
Simon Glass5e593782022-07-22 21:32:02 +053052 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -070053 return tpm2_self_test(dev, TPMI_YES);
Simon Glassbfe8fa22021-02-06 14:23:35 -070054 else
55 return -ENOSYS;
56}
57
58u32 tpm_continue_self_test(struct udevice *dev)
59{
Simon Glass5e593782022-07-22 21:32:02 +053060 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -070061 return tpm1_continue_self_test(dev);
Simon Glass5e593782022-07-22 21:32:02 +053062 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -070063 return tpm2_self_test(dev, TPMI_NO);
Simon Glassbfe8fa22021-02-06 14:23:35 -070064 else
65 return -ENOSYS;
66}
67
68u32 tpm_clear_and_reenable(struct udevice *dev)
69{
70 u32 ret;
71
72 log_info("TPM: Clear and re-enable\n");
73 ret = tpm_force_clear(dev);
74 if (ret != TPM_SUCCESS) {
75 log_err("Can't initiate a force clear\n");
76 return ret;
77 }
78
Simon Glass5e593782022-07-22 21:32:02 +053079 if (tpm_is_v1(dev)) {
Simon Glassbfe8fa22021-02-06 14:23:35 -070080 ret = tpm1_physical_enable(dev);
81 if (ret != TPM_SUCCESS) {
82 log_err("TPM: Can't set enabled state\n");
83 return ret;
84 }
85
86 ret = tpm1_physical_set_deactivated(dev, 0);
87 if (ret != TPM_SUCCESS) {
88 log_err("TPM: Can't set deactivated state\n");
89 return ret;
90 }
Simon Glassbfe8fa22021-02-06 14:23:35 -070091 }
92
93 return TPM_SUCCESS;
94}
95
96u32 tpm_nv_enable_locking(struct udevice *dev)
97{
Simon Glass5e593782022-07-22 21:32:02 +053098 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -070099 return tpm1_nv_define_space(dev, TPM_NV_INDEX_LOCK, 0, 0);
Simon Glass5e593782022-07-22 21:32:02 +0530100 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700101 return -ENOSYS;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700102 else
103 return -ENOSYS;
104}
105
106u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count)
107{
Simon Glass5e593782022-07-22 21:32:02 +0530108 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700109 return tpm1_nv_read_value(dev, index, data, count);
Simon Glass5e593782022-07-22 21:32:02 +0530110 else if (tpm_is_v2(dev))
Simon Glass6719cbe2021-02-06 14:23:40 -0700111 return tpm2_nv_read_value(dev, index, data, count);
Simon Glassbfe8fa22021-02-06 14:23:35 -0700112 else
113 return -ENOSYS;
114}
115
116u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data,
117 u32 count)
118{
Simon Glass5e593782022-07-22 21:32:02 +0530119 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700120 return tpm1_nv_write_value(dev, index, data, count);
Simon Glass5e593782022-07-22 21:32:02 +0530121 else if (tpm_is_v2(dev))
Simon Glass6719cbe2021-02-06 14:23:40 -0700122 return tpm2_nv_write_value(dev, index, data, count);
Simon Glassbfe8fa22021-02-06 14:23:35 -0700123 else
124 return -ENOSYS;
125}
126
127u32 tpm_set_global_lock(struct udevice *dev)
128{
129 return tpm_nv_write_value(dev, TPM_NV_INDEX_0, NULL, 0);
130}
131
132u32 tpm_write_lock(struct udevice *dev, u32 index)
133{
Simon Glass5e593782022-07-22 21:32:02 +0530134 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700135 return -ENOSYS;
Simon Glass5e593782022-07-22 21:32:02 +0530136 else if (tpm_is_v2(dev))
Simon Glass7785bc12021-02-06 14:23:41 -0700137 return tpm2_write_lock(dev, index);
Simon Glassbfe8fa22021-02-06 14:23:35 -0700138 else
139 return -ENOSYS;
140}
141
142u32 tpm_pcr_extend(struct udevice *dev, u32 index, const void *in_digest,
143 void *out_digest)
144{
Simon Glass5e593782022-07-22 21:32:02 +0530145 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700146 return tpm1_extend(dev, index, in_digest, out_digest);
Simon Glass5e593782022-07-22 21:32:02 +0530147 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700148 return tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, in_digest,
149 TPM2_DIGEST_LEN);
Simon Glassbfe8fa22021-02-06 14:23:35 -0700150 else
151 return -ENOSYS;
152}
153
154u32 tpm_pcr_read(struct udevice *dev, u32 index, void *data, size_t count)
155{
Simon Glass5e593782022-07-22 21:32:02 +0530156 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700157 return tpm1_pcr_read(dev, index, data, count);
Simon Glass5e593782022-07-22 21:32:02 +0530158 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700159 return -ENOSYS;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700160 else
161 return -ENOSYS;
162}
163
164u32 tpm_tsc_physical_presence(struct udevice *dev, u16 presence)
165{
Simon Glass5e593782022-07-22 21:32:02 +0530166 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700167 return tpm1_tsc_physical_presence(dev, presence);
Simon Glassb8eb9212021-02-06 14:23:37 -0700168
169 /*
170 * Nothing to do on TPM2 for this; use platform hierarchy availability
171 * instead.
172 */
Simon Glass5e593782022-07-22 21:32:02 +0530173 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700174 return 0;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700175 else
176 return -ENOSYS;
177}
178
179u32 tpm_finalise_physical_presence(struct udevice *dev)
180{
Simon Glass5e593782022-07-22 21:32:02 +0530181 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700182 return tpm1_finalise_physical_presence(dev);
Simon Glassb8eb9212021-02-06 14:23:37 -0700183
184 /* Nothing needs to be done with tpm2 */
Simon Glass5e593782022-07-22 21:32:02 +0530185 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700186 return 0;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700187 else
188 return -ENOSYS;
189}
190
191u32 tpm_read_pubek(struct udevice *dev, void *data, size_t count)
192{
Simon Glass5e593782022-07-22 21:32:02 +0530193 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700194 return tpm1_read_pubek(dev, data, count);
Simon Glass5e593782022-07-22 21:32:02 +0530195 else if (tpm_is_v2(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700196 return -ENOSYS; /* not implemented yet */
Simon Glassb8eb9212021-02-06 14:23:37 -0700197 else
198 return -ENOSYS;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700199}
200
201u32 tpm_force_clear(struct udevice *dev)
202{
Simon Glass5e593782022-07-22 21:32:02 +0530203 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700204 return tpm1_force_clear(dev);
Simon Glass5e593782022-07-22 21:32:02 +0530205 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700206 return tpm2_clear(dev, TPM2_RH_PLATFORM, NULL, 0);
Simon Glassbfe8fa22021-02-06 14:23:35 -0700207 else
208 return -ENOSYS;
209}
210
211u32 tpm_physical_enable(struct udevice *dev)
212{
Simon Glass5e593782022-07-22 21:32:02 +0530213 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700214 return tpm1_physical_enable(dev);
Simon Glassb8eb9212021-02-06 14:23:37 -0700215
216 /* Nothing needs to be done with tpm2 */
Simon Glass5e593782022-07-22 21:32:02 +0530217 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700218 return 0;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700219 else
220 return -ENOSYS;
221}
222
223u32 tpm_physical_disable(struct udevice *dev)
224{
Simon Glass5e593782022-07-22 21:32:02 +0530225 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700226 return tpm1_physical_disable(dev);
Simon Glassb8eb9212021-02-06 14:23:37 -0700227
228 /* Nothing needs to be done with tpm2 */
Simon Glass5e593782022-07-22 21:32:02 +0530229 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700230 return 0;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700231 else
232 return -ENOSYS;
233}
234
235u32 tpm_physical_set_deactivated(struct udevice *dev, u8 state)
236{
Simon Glass5e593782022-07-22 21:32:02 +0530237 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700238 return tpm1_physical_set_deactivated(dev, state);
Simon Glassb8eb9212021-02-06 14:23:37 -0700239 /* Nothing needs to be done with tpm2 */
Simon Glass5e593782022-07-22 21:32:02 +0530240 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700241 return 0;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700242 else
243 return -ENOSYS;
244}
245
246u32 tpm_get_capability(struct udevice *dev, u32 cap_area, u32 sub_cap,
247 void *cap, size_t count)
248{
Simon Glass5e593782022-07-22 21:32:02 +0530249 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700250 return tpm1_get_capability(dev, cap_area, sub_cap, cap, count);
Simon Glass5e593782022-07-22 21:32:02 +0530251 else if (tpm_is_v2(dev))
Simon Glassb8eb9212021-02-06 14:23:37 -0700252 return tpm2_get_capability(dev, cap_area, sub_cap, cap, count);
Simon Glassbfe8fa22021-02-06 14:23:35 -0700253 else
254 return -ENOSYS;
255}
256
257u32 tpm_get_permissions(struct udevice *dev, u32 index, u32 *perm)
258{
Simon Glass5e593782022-07-22 21:32:02 +0530259 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700260 return tpm1_get_permissions(dev, index, perm);
Simon Glass5e593782022-07-22 21:32:02 +0530261 else if (tpm_is_v2(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700262 return -ENOSYS; /* not implemented yet */
Simon Glassb8eb9212021-02-06 14:23:37 -0700263 else
264 return -ENOSYS;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700265}
266
267u32 tpm_get_random(struct udevice *dev, void *data, u32 count)
268{
Simon Glass5e593782022-07-22 21:32:02 +0530269 if (tpm_is_v1(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700270 return tpm1_get_random(dev, data, count);
Simon Glass5e593782022-07-22 21:32:02 +0530271 else if (tpm_is_v2(dev))
Simon Glassbfe8fa22021-02-06 14:23:35 -0700272 return -ENOSYS; /* not implemented yet */
Simon Glassb8eb9212021-02-06 14:23:37 -0700273 else
274 return -ENOSYS;
Simon Glassbfe8fa22021-02-06 14:23:35 -0700275}