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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 5fa66df63afe2841ce27596996811469903373a7 / . / board / tqm8260 / tqm8260.c
blob: a0a38caf2c5ad46f718d0ffa212b14f6b4fa0573 [file] [log] [blame]
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ioports.h>
26#include <mpc8260.h>
27
28/*
29 * I/O Port configuration table
30 *
31 * if conf is 1, then that port pin will be configured at boot time
32 * according to the five values podr/pdir/ppar/psor/pdat for that entry
33 */
34
35const iop_conf_t iop_conf_tab[4][32] = {
36
37 /* Port A configuration */
38 { /* conf ppar psor pdir podr pdat */
39 /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
40 /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
41 /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
42 /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
43 /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
44 /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
45 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
46 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
47 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
48 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
49 /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
50 /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
51 /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
52 /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
53 /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
54 /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
55 /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
56 /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
57 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
58 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
59 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
60 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
61 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
62 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
63 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
64 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
65 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
66 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
67 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
68 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
69 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
70 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
71 },
72
73 /* Port B configuration */
74 { /* conf ppar psor pdir podr pdat */
75 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
76 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
77 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
78 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
79 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
80 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
81 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
82 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
83 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
84 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
85 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
86 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
87 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
88 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
89 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
90 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
91 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
92 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
93 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
94 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
95 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
96 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
97 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
98 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
99 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
100 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
101 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
102 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
103 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
104 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
105 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
106 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
107 },
108
109 /* Port C */
110 { /* conf ppar psor pdir podr pdat */
111 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
112 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
113 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
114 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
115 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
116 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
117 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
118 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
119 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
120 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
121 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
122 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
123 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
124 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
125 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
126 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
127 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
128 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
129 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
130 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
131 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
132 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
133 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
134 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
135 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
136 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
137 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
138 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
139 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
140 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
141 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
142 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
143 },
144
145 /* Port D */
146 { /* conf ppar psor pdir podr pdat */
147 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
148 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
149 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
150 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
151 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
152 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
153 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
154 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
155 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
156 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
157 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
158 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
159 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
160 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
161 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
162 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
163#if defined(CONFIG_SOFT_I2C)
164 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
165 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
166#else
167#if defined(CONFIG_HARD_I2C)
168 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
169 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
170#else /* normal I/O port pins */
171 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
172 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
173#endif
174#endif
175 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
176 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
177 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
178 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
179 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
180 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
181 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
182 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
183 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
184 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
185 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
186 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
187 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
188 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
189 }
190};
191
192/* ------------------------------------------------------------------------- */
193
194/* Check Board Identity:
195 */
196int checkboard (void)
197{
198 unsigned char str[64];
199 int i = getenv_r ("serial#", str, sizeof (str));
200
201 puts ("Board: ");
202
wdenk4532cb62003-04-27 22:52:51 +0000[diff] [blame]203 if (!i || strncmp (str, "TQM82", 5)) {
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]204 puts ("### No HW ID - assuming TQM8260\n");
wdenk7c7a23b2002-12-07 00:20:59 +0000[diff] [blame]205 return (0);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]206 }
207
208 puts (str);
209 putc ('\n');
210
211 return 0;
212}
213
214/* ------------------------------------------------------------------------- */
215
216/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
217 *
218 * This routine performs standard 8260 initialization sequence
219 * and calculates the available memory size. It may be called
220 * several times to try different SDRAM configurations on both
221 * 60x and local buses.
222 */
223static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
224 ulong orx, volatile uchar * base)
225{
226 volatile uchar c = 0xff;
227 ulong cnt, val;
228 volatile ulong *addr;
229 volatile uint *sdmr_ptr;
230 volatile uint *orx_ptr;
231 int i;
232 ulong save[32]; /* to make test non-destructive */
wdenk5fa66df2003-10-29 23:18:55 +0000[diff] [blame^]233 ulong maxsize, size;
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]234
235 /* We must be able to test a location outsize the maximum legal size
236 * to find out THAT we are outside; but this address still has to be
237 * mapped by the controller. That means, that the initial mapping has
238 * to be (at least) twice as large as the maximum expected size.
239 */
240 maxsize = (1 + (~orx | 0x7fff)) / 2;
241
242 /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
243 * we are configuring CS1 if base != 0
244 */
245 sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
246 orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
247
248 *orx_ptr = orx;
249
250 /*
251 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
252 *
253 * "At system reset, initialization software must set up the
254 * programmable parameters in the memory controller banks registers
255 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
256 * system software should execute the following initialization sequence
257 * for each SDRAM device.
258 *
259 * 1. Issue a PRECHARGE-ALL-BANKS command
260 * 2. Issue eight CBR REFRESH commands
261 * 3. Issue a MODE-SET command to initialize the mode register
262 *
263 * The initial commands are executed by setting P/LSDMR[OP] and
264 * accessing the SDRAM with a single-byte transaction."
265 *
266 * The appropriate BRx/ORx registers have already been set when we
267 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
268 */
269
270 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
271 *base = c;
272
273 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
274 for (i = 0; i < 8; i++)
275 *base = c;
276
277 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
278 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
279
280 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
281 *base = c;
282
283 /*
284 * Check memory range for valid RAM. A simple memory test determines
285 * the actually available RAM size between addresses `base' and
286 * `base + maxsize'. Some (not all) hardware errors are detected:
287 * - short between address lines
288 * - short between data lines
289 */
290 i = 0;
291 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
292 addr = (volatile ulong *) base + cnt; /* pointer arith! */
293 save[i++] = *addr;
294 *addr = ~cnt;
295 }
296
297 addr = (volatile ulong *) base;
298 save[i] = *addr;
299 *addr = 0;
300
301 if ((val = *addr) != 0) {
wdenk5fa66df2003-10-29 23:18:55 +0000[diff] [blame^]302 /* Restore the original data before leaving the function.
303 */
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]304 *addr = save[i];
wdenk5fa66df2003-10-29 23:18:55 +0000[diff] [blame^]305 for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
306 addr = (volatile ulong *) base + cnt;
307 *addr = save[--i];
308 }
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]309 return (0);
310 }
311
312 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
313 addr = (volatile ulong *) base + cnt; /* pointer arith! */
314 val = *addr;
315 *addr = save[--i];
316 if (val != ~cnt) {
wdenk5fa66df2003-10-29 23:18:55 +0000[diff] [blame^]317 size = cnt * sizeof (long);
318 /* Restore the original data before leaving the function.
319 */
320 for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
321 addr = (volatile ulong *) base + cnt;
322 *addr = save[--i];
323 }
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]324 /* Write the actual size to ORx
325 */
wdenk5fa66df2003-10-29 23:18:55 +0000[diff] [blame^]326 *orx_ptr = orx | ~(size - 1);
327 return (size);
wdenkf8cac652002-08-26 22:36:39 +0000[diff] [blame]328 }
329 }
330 return (maxsize);
331}
332
333long int initdram (int board_type)
334{
335 volatile immap_t *immap = (immap_t *) CFG_IMMR;
336 volatile memctl8260_t *memctl = &immap->im_memctl;
337
338#ifndef CFG_RAMBOOT
339 long size8, size9;
340#endif
341 long psize, lsize;
342
343 psize = 16 * 1024 * 1024;
344 lsize = 0;
345
346 memctl->memc_psrt = CFG_PSRT;
347 memctl->memc_mptpr = CFG_MPTPR;
348
349#if 0 /* Just for debugging */
350#define prt_br_or(brX,orX) do { \
351 ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
352 ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
353 printf ("\n" \
354 #brX " 0x%08x " #orX " 0x%08x " \
355 "==> 0x%08lx ... 0x%08lx = %ld MB\n", \
356 memctl->memc_ ## brX, memctl->memc_ ## orX, \
357 start, start+sizem, (sizem+1)>>20); \
358 } while (0)
359 prt_br_or (br0, or0);
360 prt_br_or (br1, or1);
361 prt_br_or (br2, or2);
362 prt_br_or (br3, or3);
363#endif
364
365#ifndef CFG_RAMBOOT
366 /* 60x SDRAM setup:
367 */
368 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
369 (uchar *) CFG_SDRAM_BASE);
370 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
371 (uchar *) CFG_SDRAM_BASE);
372
373 if (size8 < size9) {
374 psize = size9;
375 printf ("(60x:9COL - %ld MB, ", psize >> 20);
376 } else {
377 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
378 (uchar *) CFG_SDRAM_BASE);
379 printf ("(60x:8COL - %ld MB, ", psize >> 20);
380 }
381
382 /* Local SDRAM setup:
383 */
384#ifdef CFG_INIT_LOCAL_SDRAM
385 memctl->memc_lsrt = CFG_LSRT;
386 size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
387 (uchar *) SDRAM_BASE2_PRELIM);
388 size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
389 (uchar *) SDRAM_BASE2_PRELIM);
390
391 if (size8 < size9) {
392 lsize = size9;
393 printf ("Local:9COL - %ld MB) using ", lsize >> 20);
394 } else {
395 lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
396 (uchar *) SDRAM_BASE2_PRELIM);
397 printf ("Local:8COL - %ld MB) using ", lsize >> 20);
398 }
399
400#if 0
401 /* Set up BR2 so that the local SDRAM goes
402 * right after the 60x SDRAM
403 */
404 memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
405 (CFG_SDRAM_BASE + psize);
406#endif
407#endif /* CFG_INIT_LOCAL_SDRAM */
408#endif /* CFG_RAMBOOT */
409
410 icache_enable ();
411
412 return (psize);
413}
414
415/* ------------------------------------------------------------------------- */