blob: 84d92b8d11cb08a09ae41a94d892e2d82e23a400 [file] [log] [blame]
Tero Kristo00fde6b2020-06-16 11:03:05 +03001// SPDX-License-Identifier: GPL-2.0
2&l4_cfg { /* 0x4a000000 */
3 compatible = "ti,omap4-l4-cfg", "simple-bus";
4 reg = <0x4a000000 0x800>,
5 <0x4a000800 0x800>,
6 <0x4a001000 0x1000>;
7 reg-names = "ap", "la", "ia0";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
11 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
12 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
13 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
14 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
15 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
16 <0x00300000 0x4a300000 0x080000>; /* segment 6 */
17
18 segment@0 { /* 0x4a000000 */
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
23 <0x00001000 0x00001000 0x001000>, /* ap 1 */
24 <0x00000800 0x00000800 0x000800>, /* ap 2 */
25 <0x00002000 0x00002000 0x001000>, /* ap 3 */
26 <0x00003000 0x00003000 0x001000>, /* ap 4 */
27 <0x00004000 0x00004000 0x001000>, /* ap 5 */
28 <0x00005000 0x00005000 0x001000>, /* ap 6 */
29 <0x00056000 0x00056000 0x001000>, /* ap 7 */
30 <0x00057000 0x00057000 0x001000>, /* ap 8 */
31 <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
32 <0x00058000 0x00058000 0x004000>, /* ap 10 */
33 <0x00062000 0x00062000 0x001000>, /* ap 11 */
34 <0x00063000 0x00063000 0x001000>, /* ap 12 */
35 <0x00008000 0x00008000 0x002000>, /* ap 23 */
36 <0x0000a000 0x0000a000 0x001000>, /* ap 24 */
37 <0x00066000 0x00066000 0x001000>, /* ap 25 */
38 <0x00067000 0x00067000 0x001000>, /* ap 26 */
39 <0x0005e000 0x0005e000 0x002000>, /* ap 80 */
40 <0x00060000 0x00060000 0x001000>, /* ap 81 */
41 <0x00064000 0x00064000 0x001000>, /* ap 86 */
42 <0x00065000 0x00065000 0x001000>; /* ap 87 */
43
44 target-module@2000 { /* 0x4a002000, ap 3 06.0 */
45 compatible = "ti,sysc-omap4", "ti,sysc";
46 ti,hwmods = "ctrl_module_core";
47 reg = <0x2000 0x4>,
48 <0x2010 0x4>;
49 reg-names = "rev", "sysc";
50 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
51 <SYSC_IDLE_NO>,
52 <SYSC_IDLE_SMART>,
53 <SYSC_IDLE_SMART_WKUP>;
54 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges = <0x0 0x2000 0x1000>;
58
59 omap4_scm_core: scm@0 {
60 compatible = "ti,omap4-scm-core", "simple-bus";
61 reg = <0x0 0x1000>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges = <0 0 0x1000>;
65
66 scm_conf: scm_conf@0 {
67 compatible = "syscon";
68 reg = <0x0 0x800>;
69 #address-cells = <1>;
70 #size-cells = <1>;
71 };
72
73 omap_control_usb2phy: control-phy@300 {
74 compatible = "ti,control-phy-usb2";
75 reg = <0x300 0x4>;
76 reg-names = "power";
77 };
78
79 omap_control_usbotg: control-phy@33c {
80 compatible = "ti,control-phy-otghs";
81 reg = <0x33c 0x4>;
82 reg-names = "otghs_control";
83 };
84 };
85 };
86
87 target-module@4000 { /* 0x4a004000, ap 5 02.0 */
88 compatible = "ti,sysc-omap4", "ti,sysc";
89 reg = <0x4000 0x4>;
90 reg-names = "rev";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges = <0x0 0x4000 0x1000>;
94
95 cm1: cm1@0 {
96 compatible = "ti,omap4-cm1", "simple-bus";
97 reg = <0x0 0x2000>;
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges = <0 0 0x2000>;
101
102 cm1_clocks: clocks {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 };
106
107 cm1_clockdomains: clockdomains {
108 };
109 };
110 };
111
112 target-module@8000 { /* 0x4a008000, ap 23 32.0 */
113 compatible = "ti,sysc-omap4", "ti,sysc";
114 reg = <0x8000 0x4>;
115 reg-names = "rev";
116 #address-cells = <1>;
117 #size-cells = <1>;
118 ranges = <0x0 0x8000 0x2000>;
119
120 cm2: cm2@0 {
121 compatible = "ti,omap4-cm2", "simple-bus";
122 reg = <0x0 0x2000>;
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0 0x2000>;
126
127 cm2_clocks: clocks {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 };
131
132 cm2_clockdomains: clockdomains {
133 };
134 };
135 };
136
137 target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
138 compatible = "ti,sysc-omap2", "ti,sysc";
139 reg = <0x56000 0x4>,
140 <0x5602c 0x4>,
141 <0x56028 0x4>;
142 reg-names = "rev", "sysc", "syss";
143 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
144 SYSC_OMAP2_EMUFREE |
145 SYSC_OMAP2_SOFTRESET |
146 SYSC_OMAP2_AUTOIDLE)>;
147 ti,sysc-midle = <SYSC_IDLE_FORCE>,
148 <SYSC_IDLE_NO>,
149 <SYSC_IDLE_SMART>;
150 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
151 <SYSC_IDLE_NO>,
152 <SYSC_IDLE_SMART>;
153 ti,syss-mask = <1>;
154 /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */
155 clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>;
156 clock-names = "fck";
157 #address-cells = <1>;
158 #size-cells = <1>;
159 ranges = <0x0 0x56000 0x1000>;
160
161 sdma: dma-controller@0 {
162 compatible = "ti,omap4430-sdma", "ti,omap-sdma";
163 reg = <0x0 0x1000>;
164 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
168 #dma-cells = <1>;
169 dma-channels = <32>;
170 dma-requests = <127>;
171 };
172 };
173
174 target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
175 compatible = "ti,sysc-omap2", "ti,sysc";
176 reg = <0x58000 0x4>,
177 <0x58010 0x4>,
178 <0x58014 0x4>;
179 reg-names = "rev", "sysc", "syss";
180 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
181 SYSC_OMAP2_SOFTRESET |
182 SYSC_OMAP2_AUTOIDLE)>;
183 ti,sysc-midle = <SYSC_IDLE_FORCE>,
184 <SYSC_IDLE_NO>,
185 <SYSC_IDLE_SMART>,
186 <SYSC_IDLE_SMART_WKUP>;
187 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
188 <SYSC_IDLE_NO>,
189 <SYSC_IDLE_SMART>,
190 <SYSC_IDLE_SMART_WKUP>;
191 ti,syss-mask = <1>;
192 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
193 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
194 clock-names = "fck";
195 #address-cells = <1>;
196 #size-cells = <1>;
197 ranges = <0x0 0x58000 0x5000>;
198
199 hsi: hsi@0 {
200 compatible = "ti,omap4-hsi";
201 reg = <0x0 0x4000>,
202 <0x5000 0x1000>;
203 reg-names = "sys", "gdd";
204
205 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
206 clock-names = "hsi_fck";
207
208 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
209 interrupt-names = "gdd_mpu";
210
211 #address-cells = <1>;
212 #size-cells = <1>;
213 ranges = <0 0 0x4000>;
214
215 hsi_port1: hsi-port@2000 {
216 compatible = "ti,omap4-hsi-port";
217 reg = <0x2000 0x800>,
218 <0x2800 0x800>;
219 reg-names = "tx", "rx";
220 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
221 };
222
223 hsi_port2: hsi-port@3000 {
224 compatible = "ti,omap4-hsi-port";
225 reg = <0x3000 0x800>,
226 <0x3800 0x800>;
227 reg-names = "tx", "rx";
228 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
229 };
230 };
231 };
232
233 target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */
234 compatible = "ti,sysc";
235 status = "disabled";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 ranges = <0x0 0x5e000 0x2000>;
239 };
240
241 target-module@62000 { /* 0x4a062000, ap 11 16.0 */
242 compatible = "ti,sysc-omap2", "ti,sysc";
243 ti,hwmods = "usb_tll_hs";
244 reg = <0x62000 0x4>,
245 <0x62010 0x4>,
246 <0x62014 0x4>;
247 reg-names = "rev", "sysc", "syss";
248 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
249 SYSC_OMAP2_ENAWAKEUP |
250 SYSC_OMAP2_SOFTRESET |
251 SYSC_OMAP2_AUTOIDLE)>;
252 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
253 <SYSC_IDLE_NO>,
254 <SYSC_IDLE_SMART>;
255 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
256 clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
257 clock-names = "fck";
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges = <0x0 0x62000 0x1000>;
261
262 usbhstll: usbhstll@0 {
263 compatible = "ti,usbhs-tll";
264 reg = <0x0 0x1000>;
265 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
266 };
267 };
268
269 target-module@64000 { /* 0x4a064000, ap 86 1e.0 */
270 compatible = "ti,sysc-omap4", "ti,sysc";
271 ti,hwmods = "usb_host_hs";
272 reg = <0x64000 0x4>,
273 <0x64010 0x4>,
274 <0x64014 0x4>;
275 reg-names = "rev", "sysc", "syss";
276 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
277 ti,sysc-midle = <SYSC_IDLE_FORCE>,
278 <SYSC_IDLE_NO>,
279 <SYSC_IDLE_SMART>,
280 <SYSC_IDLE_SMART_WKUP>;
281 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
282 <SYSC_IDLE_NO>,
283 <SYSC_IDLE_SMART>,
284 <SYSC_IDLE_SMART_WKUP>;
285 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
286 clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
287 clock-names = "fck";
288 #address-cells = <1>;
289 #size-cells = <1>;
290 ranges = <0x0 0x64000 0x1000>;
291
292 usbhshost: usbhshost@0 {
293 compatible = "ti,usbhs-host";
294 reg = <0x0 0x800>;
295 #address-cells = <1>;
296 #size-cells = <1>;
297 ranges = <0 0 0x1000>;
298 clocks = <&init_60m_fclk>,
299 <&xclk60mhsp1_ck>,
300 <&xclk60mhsp2_ck>;
301 clock-names = "refclk_60m_int",
302 "refclk_60m_ext_p1",
303 "refclk_60m_ext_p2";
304
305 usbhsohci: ohci@800 {
306 compatible = "ti,ohci-omap3";
307 reg = <0x800 0x400>;
308 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
309 remote-wakeup-connected;
310 };
311
312 usbhsehci: ehci@c00 {
313 compatible = "ti,ehci-omap";
314 reg = <0xc00 0x400>;
315 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
316 };
317 };
318 };
319
320 target-module@66000 { /* 0x4a066000, ap 25 26.0 */
321 compatible = "ti,sysc-omap2", "ti,sysc";
322 reg = <0x66000 0x4>,
323 <0x66010 0x4>,
324 <0x66014 0x4>;
325 reg-names = "rev", "sysc", "syss";
326 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
327 SYSC_OMAP2_SOFTRESET |
328 SYSC_OMAP2_AUTOIDLE)>;
329 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
330 <SYSC_IDLE_NO>,
331 <SYSC_IDLE_SMART>;
332 /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
333 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
334 clock-names = "fck";
335 resets = <&prm_tesla 1>;
336 reset-names = "rstctrl";
337 #address-cells = <1>;
338 #size-cells = <1>;
339 ranges = <0x0 0x66000 0x1000>;
340
341 mmu_dsp: mmu@0 {
342 compatible = "ti,omap4-iommu";
343 reg = <0x0 0x100>;
344 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
345 #iommu-cells = <0>;
346 };
347 };
348 };
349
350 segment@80000 { /* 0x4a080000 */
351 compatible = "simple-bus";
352 #address-cells = <1>;
353 #size-cells = <1>;
354 ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
355 <0x0005a000 0x000da000 0x001000>, /* ap 14 */
356 <0x0005b000 0x000db000 0x001000>, /* ap 15 */
357 <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
358 <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
359 <0x0005e000 0x000de000 0x001000>, /* ap 18 */
360 <0x00060000 0x000e0000 0x001000>, /* ap 19 */
361 <0x00061000 0x000e1000 0x001000>, /* ap 20 */
362 <0x00074000 0x000f4000 0x001000>, /* ap 27 */
363 <0x00075000 0x000f5000 0x001000>, /* ap 28 */
364 <0x00076000 0x000f6000 0x001000>, /* ap 29 */
365 <0x00077000 0x000f7000 0x001000>, /* ap 30 */
366 <0x00036000 0x000b6000 0x001000>, /* ap 69 */
367 <0x00037000 0x000b7000 0x001000>, /* ap 70 */
368 <0x0004d000 0x000cd000 0x001000>, /* ap 78 */
369 <0x0004e000 0x000ce000 0x001000>, /* ap 79 */
370 <0x00029000 0x000a9000 0x001000>, /* ap 82 */
371 <0x0002a000 0x000aa000 0x001000>, /* ap 83 */
372 <0x0002b000 0x000ab000 0x001000>, /* ap 84 */
373 <0x0002c000 0x000ac000 0x001000>, /* ap 85 */
374 <0x0002d000 0x000ad000 0x001000>, /* ap 88 */
375 <0x0002e000 0x000ae000 0x001000>; /* ap 89 */
376
377 target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */
378 compatible = "ti,sysc";
379 status = "disabled";
380 #address-cells = <1>;
381 #size-cells = <1>;
382 ranges = <0x0 0x29000 0x1000>;
383 };
384
385 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
386 compatible = "ti,sysc-omap2", "ti,sysc";
387 reg = <0x2b400 0x4>,
388 <0x2b404 0x4>,
389 <0x2b408 0x4>;
390 reg-names = "rev", "sysc", "syss";
391 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
392 SYSC_OMAP2_SOFTRESET |
393 SYSC_OMAP2_AUTOIDLE)>;
394 ti,sysc-midle = <SYSC_IDLE_FORCE>,
395 <SYSC_IDLE_NO>,
396 <SYSC_IDLE_SMART>;
397 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
398 <SYSC_IDLE_NO>,
399 <SYSC_IDLE_SMART>,
400 <SYSC_IDLE_SMART_WKUP>;
401 ti,syss-mask = <1>;
402 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
403 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
404 clock-names = "fck";
405 #address-cells = <1>;
406 #size-cells = <1>;
407 ranges = <0x0 0x2b000 0x1000>;
408
409 usb_otg_hs: usb_otg_hs@0 {
410 compatible = "ti,omap4-musb";
411 reg = <0x0 0x7ff>;
412 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
413 interrupt-names = "mc", "dma";
414 usb-phy = <&usb2_phy>;
415 phys = <&usb2_phy>;
416 phy-names = "usb2-phy";
417 multipoint = <1>;
418 num-eps = <16>;
419 ram-bits = <12>;
420 ctrl-module = <&omap_control_usbotg>;
421 };
422 };
423
424 target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
425 compatible = "ti,sysc-omap2", "ti,sysc";
426 reg = <0x2d000 0x4>,
427 <0x2d010 0x4>,
428 <0x2d014 0x4>;
429 reg-names = "rev", "sysc", "syss";
430 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
431 SYSC_OMAP2_AUTOIDLE)>;
432 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
433 <SYSC_IDLE_NO>,
434 <SYSC_IDLE_SMART>;
435 ti,syss-mask = <1>;
436 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
437 clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
438 clock-names = "fck";
439 #address-cells = <1>;
440 #size-cells = <1>;
441 ranges = <0x0 0x2d000 0x1000>;
442
443 ocp2scp@0 {
444 compatible = "ti,omap-ocp2scp";
445 reg = <0x0 0x1f>;
446 #address-cells = <1>;
447 #size-cells = <1>;
448 ranges = <0 0 0x1000>;
449 usb2_phy: usb2phy@80 {
450 compatible = "ti,omap-usb2";
451 reg = <0x80 0x58>;
452 ctrl-module = <&omap_control_usb2phy>;
453 clocks = <&usb_phy_cm_clk32k>;
454 clock-names = "wkupclk";
455 #phy-cells = <0>;
456 };
457 };
458 };
459
460 /* d2d mdm */
461 target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
462 compatible = "ti,sysc-omap2", "ti,sysc";
463 reg = <0x36000 0x4>,
464 <0x36010 0x4>,
465 <0x36014 0x4>;
466 reg-names = "rev", "sysc", "syss";
467 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
468 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
469 <SYSC_IDLE_NO>,
470 <SYSC_IDLE_SMART>,
471 <SYSC_IDLE_SMART_WKUP>;
472 ti,syss-mask = <1>;
473 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
474 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
475 clock-names = "fck";
476 #address-cells = <1>;
477 #size-cells = <1>;
478 ranges = <0x0 0x36000 0x1000>;
479 };
480
481 /* d2d mpu */
482 target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
483 compatible = "ti,sysc-omap2", "ti,sysc";
484 reg = <0x4d000 0x4>,
485 <0x4d010 0x4>,
486 <0x4d014 0x4>;
487 reg-names = "rev", "sysc", "syss";
488 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
489 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
490 <SYSC_IDLE_NO>,
491 <SYSC_IDLE_SMART>,
492 <SYSC_IDLE_SMART_WKUP>;
493 ti,syss-mask = <1>;
494 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
495 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
496 clock-names = "fck";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 ranges = <0x0 0x4d000 0x1000>;
500 };
501
502 target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
503 compatible = "ti,sysc-omap4-sr", "ti,sysc";
504 reg = <0x59038 0x4>;
505 reg-names = "sysc";
506 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
507 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
508 <SYSC_IDLE_NO>,
509 <SYSC_IDLE_SMART>,
510 <SYSC_IDLE_SMART_WKUP>;
511 /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
512 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
513 clock-names = "fck";
514 #address-cells = <1>;
515 #size-cells = <1>;
516 ranges = <0x0 0x59000 0x1000>;
517
518 smartreflex_mpu: smartreflex@0 {
519 compatible = "ti,omap4-smartreflex-mpu";
520 reg = <0x0 0x80>;
521 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
522 };
523 };
524
525 target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
526 compatible = "ti,sysc-omap4-sr", "ti,sysc";
527 reg = <0x5b038 0x4>;
528 reg-names = "sysc";
529 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
530 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
531 <SYSC_IDLE_NO>,
532 <SYSC_IDLE_SMART>,
533 <SYSC_IDLE_SMART_WKUP>;
534 /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
535 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
536 clock-names = "fck";
537 #address-cells = <1>;
538 #size-cells = <1>;
539 ranges = <0x0 0x5b000 0x1000>;
540
541 smartreflex_iva: smartreflex@0 {
542 compatible = "ti,omap4-smartreflex-iva";
543 reg = <0x0 0x80>;
544 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
545 };
546 };
547
548 target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
549 compatible = "ti,sysc-omap4-sr", "ti,sysc";
550 reg = <0x5d038 0x4>;
551 reg-names = "sysc";
552 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
553 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
554 <SYSC_IDLE_NO>,
555 <SYSC_IDLE_SMART>,
556 <SYSC_IDLE_SMART_WKUP>;
557 /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
558 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
559 clock-names = "fck";
560 #address-cells = <1>;
561 #size-cells = <1>;
562 ranges = <0x0 0x5d000 0x1000>;
563
564 smartreflex_core: smartreflex@0 {
565 compatible = "ti,omap4-smartreflex-core";
566 reg = <0x0 0x80>;
567 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
568 };
569 };
570
571 target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */
572 compatible = "ti,sysc";
573 status = "disabled";
574 #address-cells = <1>;
575 #size-cells = <1>;
576 ranges = <0x0 0x60000 0x1000>;
577 };
578
579 target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
580 compatible = "ti,sysc-omap4", "ti,sysc";
581 reg = <0x74000 0x4>,
582 <0x74010 0x4>;
583 reg-names = "rev", "sysc";
584 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
585 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
586 <SYSC_IDLE_NO>,
587 <SYSC_IDLE_SMART>;
588 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
589 clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
590 clock-names = "fck";
591 #address-cells = <1>;
592 #size-cells = <1>;
593 ranges = <0x0 0x74000 0x1000>;
594
595 mailbox: mailbox@0 {
596 compatible = "ti,omap4-mailbox";
597 reg = <0x0 0x200>;
598 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
599 #mbox-cells = <1>;
600 ti,mbox-num-users = <3>;
601 ti,mbox-num-fifos = <8>;
Andrew Davisa39f2a52023-04-11 13:25:08 -0500602 mbox_ipu: mbox-ipu {
Tero Kristo00fde6b2020-06-16 11:03:05 +0300603 ti,mbox-tx = <0 0 0>;
604 ti,mbox-rx = <1 0 0>;
605 };
Andrew Davisa39f2a52023-04-11 13:25:08 -0500606 mbox_dsp: mbox-dsp {
Tero Kristo00fde6b2020-06-16 11:03:05 +0300607 ti,mbox-tx = <3 0 0>;
608 ti,mbox-rx = <2 0 0>;
609 };
610 };
611 };
612
613 target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
614 compatible = "ti,sysc-omap2", "ti,sysc";
615 reg = <0x76000 0x4>,
616 <0x76010 0x4>,
617 <0x76014 0x4>;
618 reg-names = "rev", "sysc", "syss";
619 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
620 SYSC_OMAP2_ENAWAKEUP |
621 SYSC_OMAP2_SOFTRESET |
622 SYSC_OMAP2_AUTOIDLE)>;
623 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
624 <SYSC_IDLE_NO>,
625 <SYSC_IDLE_SMART>;
626 ti,syss-mask = <1>;
627 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
628 clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
629 clock-names = "fck";
630 #address-cells = <1>;
631 #size-cells = <1>;
632 ranges = <0x0 0x76000 0x1000>;
633
634 hwspinlock: spinlock@0 {
635 compatible = "ti,omap4-hwspinlock";
636 reg = <0x0 0x1000>;
637 #hwlock-cells = <1>;
638 };
639 };
640 };
641
642 segment@100000 { /* 0x4a100000 */
643 compatible = "simple-bus";
644 #address-cells = <1>;
645 #size-cells = <1>;
646 ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
647 <0x00001000 0x00101000 0x001000>, /* ap 22 */
648 <0x00002000 0x00102000 0x001000>, /* ap 61 */
649 <0x00003000 0x00103000 0x001000>, /* ap 62 */
650 <0x00008000 0x00108000 0x001000>, /* ap 63 */
651 <0x00009000 0x00109000 0x001000>, /* ap 64 */
652 <0x0000a000 0x0010a000 0x001000>, /* ap 65 */
653 <0x0000b000 0x0010b000 0x001000>; /* ap 66 */
654
655 target-module@0 { /* 0x4a100000, ap 21 2a.0 */
656 compatible = "ti,sysc-omap4", "ti,sysc";
657 ti,hwmods = "ctrl_module_pad_core";
658 reg = <0x0 0x4>,
659 <0x10 0x4>;
660 reg-names = "rev", "sysc";
661 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
662 <SYSC_IDLE_NO>,
663 <SYSC_IDLE_SMART>,
664 <SYSC_IDLE_SMART_WKUP>;
665 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
666 #address-cells = <1>;
667 #size-cells = <1>;
668 ranges = <0x0 0x0 0x1000>;
669
670 omap4_pmx_core: pinmux@40 {
671 compatible = "ti,omap4-padconf",
672 "pinctrl-single";
673 reg = <0x40 0x0196>;
674 #address-cells = <1>;
675 #size-cells = <0>;
676 #pinctrl-cells = <1>;
677 #interrupt-cells = <1>;
678 interrupt-controller;
679 pinctrl-single,register-width = <16>;
680 pinctrl-single,function-mask = <0x7fff>;
681 };
682
683 omap4_padconf_global: omap4_padconf_global@5a0 {
684 compatible = "syscon",
685 "simple-bus";
686 reg = <0x5a0 0x170>;
687 #address-cells = <1>;
688 #size-cells = <1>;
689 ranges = <0 0x5a0 0x170>;
690
691 pbias_regulator: pbias_regulator@60 {
692 compatible = "ti,pbias-omap4", "ti,pbias-omap";
693 reg = <0x60 0x4>;
694 syscon = <&omap4_padconf_global>;
695 pbias_mmc_reg: pbias_mmc_omap4 {
696 regulator-name = "pbias_mmc_omap4";
697 regulator-min-microvolt = <1800000>;
698 regulator-max-microvolt = <3000000>;
699 };
700 };
701 };
702 };
703
704 target-module@2000 { /* 0x4a102000, ap 61 3c.0 */
705 compatible = "ti,sysc";
706 status = "disabled";
707 #address-cells = <1>;
708 #size-cells = <1>;
709 ranges = <0x0 0x2000 0x1000>;
710 };
711
712 target-module@8000 { /* 0x4a108000, ap 63 62.0 */
713 compatible = "ti,sysc";
714 status = "disabled";
715 #address-cells = <1>;
716 #size-cells = <1>;
717 ranges = <0x0 0x8000 0x1000>;
718 };
719
720 target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
721 compatible = "ti,sysc-omap4", "ti,sysc";
722 reg = <0xa000 0x4>,
723 <0xa010 0x4>;
724 reg-names = "rev", "sysc";
725 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
726 ti,sysc-midle = <SYSC_IDLE_FORCE>,
727 <SYSC_IDLE_NO>,
728 <SYSC_IDLE_SMART>;
729 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
730 <SYSC_IDLE_NO>,
731 <SYSC_IDLE_SMART>;
732 ti,sysc-delay-us = <2>;
733 /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */
734 clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
735 clock-names = "fck";
736 #address-cells = <1>;
737 #size-cells = <1>;
738 ranges = <0x0 0xa000 0x1000>;
739
740 /* No child device binding or driver in mainline */
741 };
742 };
743
744 segment@180000 { /* 0x4a180000 */
745 compatible = "simple-bus";
746 #address-cells = <1>;
747 #size-cells = <1>;
748 };
749
750 segment@200000 { /* 0x4a200000 */
751 compatible = "simple-bus";
752 #address-cells = <1>;
753 #size-cells = <1>;
754 ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
755 <0x0001f000 0x0021f000 0x001000>, /* ap 32 */
756 <0x0000a000 0x0020a000 0x001000>, /* ap 33 */
757 <0x0000b000 0x0020b000 0x001000>, /* ap 34 */
758 <0x00004000 0x00204000 0x001000>, /* ap 35 */
759 <0x00005000 0x00205000 0x001000>, /* ap 36 */
760 <0x00006000 0x00206000 0x001000>, /* ap 37 */
761 <0x00007000 0x00207000 0x001000>, /* ap 38 */
762 <0x00012000 0x00212000 0x001000>, /* ap 39 */
763 <0x00013000 0x00213000 0x001000>, /* ap 40 */
764 <0x0000c000 0x0020c000 0x001000>, /* ap 41 */
765 <0x0000d000 0x0020d000 0x001000>, /* ap 42 */
766 <0x00010000 0x00210000 0x001000>, /* ap 43 */
767 <0x00011000 0x00211000 0x001000>, /* ap 44 */
768 <0x00016000 0x00216000 0x001000>, /* ap 45 */
769 <0x00017000 0x00217000 0x001000>, /* ap 46 */
770 <0x00014000 0x00214000 0x001000>, /* ap 47 */
771 <0x00015000 0x00215000 0x001000>, /* ap 48 */
772 <0x00018000 0x00218000 0x001000>, /* ap 49 */
773 <0x00019000 0x00219000 0x001000>, /* ap 50 */
774 <0x00020000 0x00220000 0x001000>, /* ap 51 */
775 <0x00021000 0x00221000 0x001000>, /* ap 52 */
776 <0x00026000 0x00226000 0x001000>, /* ap 53 */
777 <0x00027000 0x00227000 0x001000>, /* ap 54 */
778 <0x00028000 0x00228000 0x001000>, /* ap 55 */
779 <0x00029000 0x00229000 0x001000>, /* ap 56 */
780 <0x0002a000 0x0022a000 0x001000>, /* ap 57 */
781 <0x0002b000 0x0022b000 0x001000>, /* ap 58 */
782 <0x0001c000 0x0021c000 0x001000>, /* ap 59 */
783 <0x0001d000 0x0021d000 0x001000>; /* ap 60 */
784
785 target-module@4000 { /* 0x4a204000, ap 35 42.0 */
786 compatible = "ti,sysc";
787 status = "disabled";
788 #address-cells = <1>;
789 #size-cells = <1>;
790 ranges = <0x0 0x4000 0x1000>;
791 };
792
793 target-module@6000 { /* 0x4a206000, ap 37 4a.0 */
794 compatible = "ti,sysc";
795 status = "disabled";
796 #address-cells = <1>;
797 #size-cells = <1>;
798 ranges = <0x0 0x6000 0x1000>;
799 };
800
801 target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */
802 compatible = "ti,sysc";
803 status = "disabled";
804 #address-cells = <1>;
805 #size-cells = <1>;
806 ranges = <0x0 0xa000 0x1000>;
807 };
808
809 target-module@c000 { /* 0x4a20c000, ap 41 20.0 */
810 compatible = "ti,sysc";
811 status = "disabled";
812 #address-cells = <1>;
813 #size-cells = <1>;
814 ranges = <0x0 0xc000 0x1000>;
815 };
816
817 target-module@10000 { /* 0x4a210000, ap 43 52.0 */
818 compatible = "ti,sysc";
819 status = "disabled";
820 #address-cells = <1>;
821 #size-cells = <1>;
822 ranges = <0x0 0x10000 0x1000>;
823 };
824
825 target-module@12000 { /* 0x4a212000, ap 39 18.0 */
826 compatible = "ti,sysc";
827 status = "disabled";
828 #address-cells = <1>;
829 #size-cells = <1>;
830 ranges = <0x0 0x12000 0x1000>;
831 };
832
833 target-module@14000 { /* 0x4a214000, ap 47 30.0 */
834 compatible = "ti,sysc";
835 status = "disabled";
836 #address-cells = <1>;
837 #size-cells = <1>;
838 ranges = <0x0 0x14000 0x1000>;
839 };
840
841 target-module@16000 { /* 0x4a216000, ap 45 28.0 */
842 compatible = "ti,sysc";
843 status = "disabled";
844 #address-cells = <1>;
845 #size-cells = <1>;
846 ranges = <0x0 0x16000 0x1000>;
847 };
848
849 target-module@18000 { /* 0x4a218000, ap 49 38.0 */
850 compatible = "ti,sysc";
851 status = "disabled";
852 #address-cells = <1>;
853 #size-cells = <1>;
854 ranges = <0x0 0x18000 0x1000>;
855 };
856
857 target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */
858 compatible = "ti,sysc";
859 status = "disabled";
860 #address-cells = <1>;
861 #size-cells = <1>;
862 ranges = <0x0 0x1c000 0x1000>;
863 };
864
865 target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */
866 compatible = "ti,sysc";
867 status = "disabled";
868 #address-cells = <1>;
869 #size-cells = <1>;
870 ranges = <0x0 0x1e000 0x1000>;
871 };
872
873 target-module@20000 { /* 0x4a220000, ap 51 40.0 */
874 compatible = "ti,sysc";
875 status = "disabled";
876 #address-cells = <1>;
877 #size-cells = <1>;
878 ranges = <0x0 0x20000 0x1000>;
879 };
880
881 target-module@26000 { /* 0x4a226000, ap 53 34.0 */
882 compatible = "ti,sysc";
883 status = "disabled";
884 #address-cells = <1>;
885 #size-cells = <1>;
886 ranges = <0x0 0x26000 0x1000>;
887 };
888
889 target-module@28000 { /* 0x4a228000, ap 55 2e.0 */
890 compatible = "ti,sysc";
891 status = "disabled";
892 #address-cells = <1>;
893 #size-cells = <1>;
894 ranges = <0x0 0x28000 0x1000>;
895 };
896
897 target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */
898 compatible = "ti,sysc";
899 status = "disabled";
900 #address-cells = <1>;
901 #size-cells = <1>;
902 ranges = <0x0 0x2a000 0x1000>;
903 };
904 };
905
906 segment@280000 { /* 0x4a280000 */
907 compatible = "simple-bus";
908 #address-cells = <1>;
909 #size-cells = <1>;
910 };
911
912 l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
913 compatible = "simple-bus";
914 #address-cells = <1>;
915 #size-cells = <1>;
916 ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
917 <0x00040000 0x00340000 0x001000>, /* ap 68 */
918 <0x00020000 0x00320000 0x004000>, /* ap 71 */
919 <0x00024000 0x00324000 0x002000>, /* ap 72 */
920 <0x00026000 0x00326000 0x001000>, /* ap 73 */
921 <0x00027000 0x00327000 0x001000>, /* ap 74 */
922 <0x00028000 0x00328000 0x001000>, /* ap 75 */
923 <0x00029000 0x00329000 0x001000>, /* ap 76 */
924 <0x00030000 0x00330000 0x010000>, /* ap 77 */
925 <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
926 <0x0002c000 0x0032c000 0x004000>; /* ap 91 */
927
928 l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */
929 compatible = "ti,sysc";
930 status = "disabled";
931 #address-cells = <1>;
932 #size-cells = <1>;
933 ranges = <0x00000000 0x00000000 0x00020000>,
934 <0x00020000 0x00020000 0x00004000>,
935 <0x00024000 0x00024000 0x00002000>,
936 <0x00026000 0x00026000 0x00001000>,
937 <0x00027000 0x00027000 0x00001000>,
938 <0x00028000 0x00028000 0x00001000>,
939 <0x00029000 0x00029000 0x00001000>,
940 <0x0002a000 0x0002a000 0x00002000>,
941 <0x0002c000 0x0002c000 0x00004000>,
942 <0x00030000 0x00030000 0x00010000>;
943 };
944 };
945};
946
947&l4_wkup { /* 0x4a300000 */
948 compatible = "ti,omap4-l4-wkup", "simple-bus";
949 reg = <0x4a300000 0x800>,
950 <0x4a300800 0x800>,
951 <0x4a301000 0x1000>;
952 reg-names = "ap", "la", "ia0";
953 #address-cells = <1>;
954 #size-cells = <1>;
955 ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */
956 <0x00010000 0x4a310000 0x010000>, /* segment 1 */
957 <0x00020000 0x4a320000 0x010000>; /* segment 2 */
958
959 segment@0 { /* 0x4a300000 */
960 compatible = "simple-bus";
961 #address-cells = <1>;
962 #size-cells = <1>;
963 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
964 <0x00001000 0x00001000 0x001000>, /* ap 1 */
965 <0x00000800 0x00000800 0x000800>, /* ap 2 */
966 <0x00006000 0x00006000 0x002000>, /* ap 3 */
967 <0x00008000 0x00008000 0x001000>, /* ap 4 */
968 <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
969 <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
970 <0x00004000 0x00004000 0x001000>, /* ap 17 */
971 <0x00005000 0x00005000 0x001000>, /* ap 18 */
972 <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
973 <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
974
975 target-module@4000 { /* 0x4a304000, ap 17 24.0 */
976 compatible = "ti,sysc-omap2", "ti,sysc";
977 ti,hwmods = "counter_32k";
978 reg = <0x4000 0x4>,
979 <0x4004 0x4>;
980 reg-names = "rev", "sysc";
981 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
982 <SYSC_IDLE_NO>;
983 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
984 clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
985 clock-names = "fck";
986 #address-cells = <1>;
987 #size-cells = <1>;
988 ranges = <0x0 0x4000 0x1000>;
989
990 counter32k: counter@0 {
991 compatible = "ti,omap-counter32k";
992 reg = <0x0 0x20>;
993 };
994 };
995
996 target-module@6000 { /* 0x4a306000, ap 3 08.0 */
997 compatible = "ti,sysc-omap4", "ti,sysc";
998 reg = <0x6000 0x4>;
999 reg-names = "rev";
1000 #address-cells = <1>;
1001 #size-cells = <1>;
1002 ranges = <0x0 0x6000 0x2000>;
1003
1004 prm: prm@0 {
1005 compatible = "ti,omap4-prm", "simple-bus";
1006 reg = <0x0 0x2000>;
1007 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1008 #address-cells = <1>;
1009 #size-cells = <1>;
1010 ranges = <0 0 0x2000>;
1011
1012 prm_clocks: clocks {
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1015 };
1016
1017 prm_clockdomains: clockdomains {
1018 };
1019 };
1020 };
1021
1022 target-module@a000 { /* 0x4a30a000, ap 15 34.0 */
1023 compatible = "ti,sysc-omap4", "ti,sysc";
1024 reg = <0xa000 0x4>;
1025 reg-names = "rev";
1026 #address-cells = <1>;
1027 #size-cells = <1>;
1028 ranges = <0x0 0xa000 0x1000>;
1029
1030 scrm: scrm@0 {
1031 compatible = "ti,omap4-scrm";
1032 reg = <0x0 0x2000>;
1033
1034 scrm_clocks: clocks {
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 };
1038
1039 scrm_clockdomains: clockdomains {
1040 };
1041 };
1042 };
1043
1044 target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */
1045 compatible = "ti,sysc-omap4", "ti,sysc";
1046 ti,hwmods = "ctrl_module_wkup";
1047 reg = <0xc000 0x4>,
1048 <0xc010 0x4>;
1049 reg-names = "rev", "sysc";
1050 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1051 <SYSC_IDLE_NO>,
1052 <SYSC_IDLE_SMART>,
1053 <SYSC_IDLE_SMART_WKUP>;
1054 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1055 #address-cells = <1>;
1056 #size-cells = <1>;
1057 ranges = <0x0 0xc000 0x1000>;
1058
1059 omap4_scm_wkup: scm@c000 {
1060 compatible = "ti,omap4-scm-wkup";
1061 reg = <0xc000 0x1000>;
1062 };
1063 };
1064 };
1065
1066 segment@10000 { /* 0x4a310000 */
1067 compatible = "simple-bus";
1068 #address-cells = <1>;
1069 #size-cells = <1>;
1070 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
1071 <0x00001000 0x00011000 0x001000>, /* ap 6 */
1072 <0x00004000 0x00014000 0x001000>, /* ap 7 */
1073 <0x00005000 0x00015000 0x001000>, /* ap 8 */
1074 <0x00008000 0x00018000 0x001000>, /* ap 9 */
1075 <0x00009000 0x00019000 0x001000>, /* ap 10 */
1076 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
1077 <0x0000d000 0x0001d000 0x001000>, /* ap 12 */
1078 <0x0000e000 0x0001e000 0x001000>, /* ap 21 */
1079 <0x0000f000 0x0001f000 0x001000>; /* ap 22 */
1080
1081 gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */
1082 compatible = "ti,sysc-omap2", "ti,sysc";
1083 reg = <0x0 0x4>,
1084 <0x10 0x4>,
1085 <0x114 0x4>;
1086 reg-names = "rev", "sysc", "syss";
1087 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1088 SYSC_OMAP2_SOFTRESET |
1089 SYSC_OMAP2_AUTOIDLE)>;
1090 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1091 <SYSC_IDLE_NO>,
1092 <SYSC_IDLE_SMART>,
1093 <SYSC_IDLE_SMART_WKUP>;
1094 ti,syss-mask = <1>;
1095 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1096 clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>,
1097 <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>;
1098 clock-names = "fck", "dbclk";
1099 #address-cells = <1>;
1100 #size-cells = <1>;
1101 ranges = <0x0 0x0 0x1000>;
1102
1103 gpio1: gpio@0 {
1104 compatible = "ti,omap4-gpio";
1105 reg = <0x0 0x200>;
1106 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1107 ti,gpio-always-on;
1108 gpio-controller;
1109 #gpio-cells = <2>;
1110 interrupt-controller;
1111 #interrupt-cells = <2>;
1112 };
1113 };
1114
1115 target-module@4000 { /* 0x4a314000, ap 7 18.0 */
1116 compatible = "ti,sysc-omap2", "ti,sysc";
1117 reg = <0x4000 0x4>,
1118 <0x4010 0x4>,
1119 <0x4014 0x4>;
1120 reg-names = "rev", "sysc", "syss";
1121 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
1122 SYSC_OMAP2_SOFTRESET)>;
1123 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1124 <SYSC_IDLE_NO>,
1125 <SYSC_IDLE_SMART>,
1126 <SYSC_IDLE_SMART_WKUP>;
1127 ti,syss-mask = <1>;
1128 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1129 clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
1130 clock-names = "fck";
1131 #address-cells = <1>;
1132 #size-cells = <1>;
1133 ranges = <0x0 0x4000 0x1000>;
1134
1135 wdt2: wdt@0 {
1136 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
1137 reg = <0x0 0x80>;
1138 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1139 };
1140 };
1141
1142 target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
1143 compatible = "ti,sysc-omap2-timer", "ti,sysc";
1144 ti,hwmods = "timer1";
1145 reg = <0x8000 0x4>,
1146 <0x8010 0x4>,
1147 <0x8014 0x4>;
1148 reg-names = "rev", "sysc", "syss";
1149 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1150 SYSC_OMAP2_EMUFREE |
1151 SYSC_OMAP2_ENAWAKEUP |
1152 SYSC_OMAP2_SOFTRESET |
1153 SYSC_OMAP2_AUTOIDLE)>;
1154 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1155 <SYSC_IDLE_NO>,
1156 <SYSC_IDLE_SMART>;
1157 ti,syss-mask = <1>;
1158 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1159 clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
1160 clock-names = "fck";
1161 #address-cells = <1>;
1162 #size-cells = <1>;
1163 ranges = <0x0 0x8000 0x1000>;
1164
1165 timer1: timer@0 {
1166 compatible = "ti,omap3430-timer";
1167 reg = <0x0 0x80>;
1168 clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
1169 clock-names = "fck";
1170 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1171 ti,timer-alwon;
1172 };
1173 };
1174
1175 target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
1176 compatible = "ti,sysc-omap2", "ti,sysc";
1177 reg = <0xc000 0x4>,
1178 <0xc010 0x4>,
1179 <0xc014 0x4>;
1180 reg-names = "rev", "sysc", "syss";
1181 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1182 SYSC_OMAP2_EMUFREE |
1183 SYSC_OMAP2_ENAWAKEUP |
1184 SYSC_OMAP2_SOFTRESET |
1185 SYSC_OMAP2_AUTOIDLE)>;
1186 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1187 <SYSC_IDLE_NO>,
1188 <SYSC_IDLE_SMART>;
1189 ti,syss-mask = <1>;
1190 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1191 clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
1192 clock-names = "fck";
1193 #address-cells = <1>;
1194 #size-cells = <1>;
1195 ranges = <0x0 0xc000 0x1000>;
1196
1197 keypad: keypad@0 {
1198 compatible = "ti,omap4-keypad";
1199 reg = <0x0 0x80>;
1200 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1201 reg-names = "mpu";
1202 };
1203 };
1204
1205 target-module@e000 { /* 0x4a31e000, ap 21 30.0 */
1206 compatible = "ti,sysc-omap4", "ti,sysc";
1207 ti,hwmods = "ctrl_module_pad_wkup";
1208 reg = <0xe000 0x4>,
1209 <0xe010 0x4>;
1210 reg-names = "rev", "sysc";
1211 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1212 <SYSC_IDLE_NO>,
1213 <SYSC_IDLE_SMART>,
1214 <SYSC_IDLE_SMART_WKUP>;
1215 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1216 #address-cells = <1>;
1217 #size-cells = <1>;
1218 ranges = <0x0 0xe000 0x1000>;
1219
1220 omap4_pmx_wkup: pinmux@40 {
1221 compatible = "ti,omap4-padconf",
1222 "pinctrl-single";
1223 reg = <0x40 0x0038>;
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226 #pinctrl-cells = <1>;
1227 #interrupt-cells = <1>;
1228 interrupt-controller;
1229 pinctrl-single,register-width = <16>;
1230 pinctrl-single,function-mask = <0x7fff>;
1231 };
1232 };
1233 };
1234
1235 segment@20000 { /* 0x4a320000 */
1236 compatible = "simple-bus";
1237 #address-cells = <1>;
1238 #size-cells = <1>;
1239 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
1240 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
1241 <0x00000000 0x00020000 0x001000>, /* ap 23 */
1242 <0x00001000 0x00021000 0x001000>, /* ap 24 */
1243 <0x00002000 0x00022000 0x001000>, /* ap 25 */
1244 <0x00003000 0x00023000 0x001000>, /* ap 26 */
1245 <0x00004000 0x00024000 0x001000>, /* ap 27 */
1246 <0x00005000 0x00025000 0x001000>, /* ap 28 */
1247 <0x00007000 0x00027000 0x000400>, /* ap 29 */
1248 <0x00008000 0x00028000 0x000800>, /* ap 30 */
1249 <0x00009000 0x00029000 0x000400>; /* ap 31 */
1250
1251 target-module@0 { /* 0x4a320000, ap 23 04.0 */
1252 compatible = "ti,sysc";
1253 status = "disabled";
1254 #address-cells = <1>;
1255 #size-cells = <1>;
1256 ranges = <0x0 0x0 0x1000>;
1257 };
1258
1259 target-module@2000 { /* 0x4a322000, ap 25 0c.0 */
1260 compatible = "ti,sysc";
1261 status = "disabled";
1262 #address-cells = <1>;
1263 #size-cells = <1>;
1264 ranges = <0x0 0x2000 0x1000>;
1265 };
1266
1267 target-module@4000 { /* 0x4a324000, ap 27 10.0 */
1268 compatible = "ti,sysc";
1269 status = "disabled";
1270 #address-cells = <1>;
1271 #size-cells = <1>;
1272 ranges = <0x0 0x4000 0x1000>;
1273 };
1274
1275 target-module@6000 { /* 0x4a326000, ap 13 28.0 */
1276 compatible = "ti,sysc";
1277 status = "disabled";
1278 #address-cells = <1>;
1279 #size-cells = <1>;
1280 ranges = <0x00000000 0x00006000 0x00001000>,
1281 <0x00001000 0x00007000 0x00000400>,
1282 <0x00002000 0x00008000 0x00000800>,
1283 <0x00003000 0x00009000 0x00000400>;
1284 };
1285 };
1286};
1287
1288&l4_per { /* 0x48000000 */
1289 compatible = "ti,omap4-l4-per", "simple-bus";
1290 reg = <0x48000000 0x800>,
1291 <0x48000800 0x800>,
1292 <0x48001000 0x400>,
1293 <0x48001400 0x400>,
1294 <0x48001800 0x400>,
1295 <0x48001c00 0x400>;
1296 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1297 #address-cells = <1>;
1298 #size-cells = <1>;
1299 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1300 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1301
1302 segment@0 { /* 0x48000000 */
1303 compatible = "simple-bus";
1304 #address-cells = <1>;
1305 #size-cells = <1>;
1306 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1307 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1308 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1309 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1310 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1311 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1312 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1313 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1314 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1315 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1316 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1317 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1318 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1319 <0x00040000 0x00040000 0x010000>, /* ap 13 */
1320 <0x00050000 0x00050000 0x001000>, /* ap 14 */
1321 <0x00055000 0x00055000 0x001000>, /* ap 15 */
1322 <0x00056000 0x00056000 0x001000>, /* ap 16 */
1323 <0x00057000 0x00057000 0x001000>, /* ap 17 */
1324 <0x00058000 0x00058000 0x001000>, /* ap 18 */
1325 <0x00059000 0x00059000 0x001000>, /* ap 19 */
1326 <0x0005a000 0x0005a000 0x001000>, /* ap 20 */
1327 <0x0005b000 0x0005b000 0x001000>, /* ap 21 */
1328 <0x0005c000 0x0005c000 0x001000>, /* ap 22 */
1329 <0x0005d000 0x0005d000 0x001000>, /* ap 23 */
1330 <0x0005e000 0x0005e000 0x001000>, /* ap 24 */
1331 <0x00060000 0x00060000 0x001000>, /* ap 25 */
1332 <0x0006a000 0x0006a000 0x001000>, /* ap 26 */
1333 <0x0006b000 0x0006b000 0x001000>, /* ap 27 */
1334 <0x0006c000 0x0006c000 0x001000>, /* ap 28 */
1335 <0x0006d000 0x0006d000 0x001000>, /* ap 29 */
1336 <0x0006e000 0x0006e000 0x001000>, /* ap 30 */
1337 <0x0006f000 0x0006f000 0x001000>, /* ap 31 */
1338 <0x00070000 0x00070000 0x001000>, /* ap 32 */
1339 <0x00071000 0x00071000 0x001000>, /* ap 33 */
1340 <0x00072000 0x00072000 0x001000>, /* ap 34 */
1341 <0x00073000 0x00073000 0x001000>, /* ap 35 */
1342 <0x00061000 0x00061000 0x001000>, /* ap 36 */
1343 <0x00096000 0x00096000 0x001000>, /* ap 37 */
1344 <0x00097000 0x00097000 0x001000>, /* ap 38 */
1345 <0x00076000 0x00076000 0x001000>, /* ap 39 */
1346 <0x00077000 0x00077000 0x001000>, /* ap 40 */
1347 <0x00078000 0x00078000 0x001000>, /* ap 41 */
1348 <0x00079000 0x00079000 0x001000>, /* ap 42 */
1349 <0x00086000 0x00086000 0x001000>, /* ap 43 */
1350 <0x00087000 0x00087000 0x001000>, /* ap 44 */
1351 <0x00088000 0x00088000 0x001000>, /* ap 45 */
1352 <0x00089000 0x00089000 0x001000>, /* ap 46 */
1353 <0x000b0000 0x000b0000 0x001000>, /* ap 47 */
1354 <0x000b1000 0x000b1000 0x001000>, /* ap 48 */
1355 <0x00098000 0x00098000 0x001000>, /* ap 49 */
1356 <0x00099000 0x00099000 0x001000>, /* ap 50 */
1357 <0x0009a000 0x0009a000 0x001000>, /* ap 51 */
1358 <0x0009b000 0x0009b000 0x001000>, /* ap 52 */
1359 <0x0009c000 0x0009c000 0x001000>, /* ap 53 */
1360 <0x0009d000 0x0009d000 0x001000>, /* ap 54 */
1361 <0x0009e000 0x0009e000 0x001000>, /* ap 55 */
1362 <0x0009f000 0x0009f000 0x001000>, /* ap 56 */
1363 <0x00090000 0x00090000 0x002000>, /* ap 57 */
1364 <0x00092000 0x00092000 0x001000>, /* ap 58 */
1365 <0x000a4000 0x000a4000 0x001000>, /* ap 59 */
1366 <0x000a6000 0x000a6000 0x001000>, /* ap 60 */
1367 <0x000a8000 0x000a8000 0x004000>, /* ap 61 */
1368 <0x000ac000 0x000ac000 0x001000>, /* ap 62 */
1369 <0x000ad000 0x000ad000 0x001000>, /* ap 63 */
1370 <0x000ae000 0x000ae000 0x001000>, /* ap 64 */
1371 <0x000b2000 0x000b2000 0x001000>, /* ap 65 */
1372 <0x000b3000 0x000b3000 0x001000>, /* ap 66 */
1373 <0x000b4000 0x000b4000 0x001000>, /* ap 67 */
1374 <0x000b5000 0x000b5000 0x001000>, /* ap 68 */
1375 <0x000b8000 0x000b8000 0x001000>, /* ap 69 */
1376 <0x000b9000 0x000b9000 0x001000>, /* ap 70 */
1377 <0x000ba000 0x000ba000 0x001000>, /* ap 71 */
1378 <0x000bb000 0x000bb000 0x001000>, /* ap 72 */
1379 <0x000d1000 0x000d1000 0x001000>, /* ap 73 */
1380 <0x000d2000 0x000d2000 0x001000>, /* ap 74 */
1381 <0x000d5000 0x000d5000 0x001000>, /* ap 75 */
1382 <0x000d6000 0x000d6000 0x001000>, /* ap 76 */
1383 <0x000a2000 0x000a2000 0x001000>, /* ap 79 */
1384 <0x000a3000 0x000a3000 0x001000>, /* ap 80 */
1385 <0x00001400 0x00001400 0x000400>, /* ap 81 */
1386 <0x00001800 0x00001800 0x000400>, /* ap 82 */
1387 <0x00001c00 0x00001c00 0x000400>, /* ap 83 */
1388 <0x000a5000 0x000a5000 0x001000>; /* ap 84 */
1389
1390 target-module@20000 { /* 0x48020000, ap 3 06.0 */
1391 compatible = "ti,sysc-omap2", "ti,sysc";
1392 reg = <0x20050 0x4>,
1393 <0x20054 0x4>,
1394 <0x20058 0x4>;
1395 reg-names = "rev", "sysc", "syss";
1396 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1397 SYSC_OMAP2_SOFTRESET |
1398 SYSC_OMAP2_AUTOIDLE)>;
1399 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1400 <SYSC_IDLE_NO>,
1401 <SYSC_IDLE_SMART>,
1402 <SYSC_IDLE_SMART_WKUP>;
1403 ti,syss-mask = <1>;
1404 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1405 clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
1406 clock-names = "fck";
1407 #address-cells = <1>;
1408 #size-cells = <1>;
1409 ranges = <0x0 0x20000 0x1000>;
1410
1411 uart3: serial@0 {
1412 compatible = "ti,omap4-uart";
1413 reg = <0x0 0x100>;
1414 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1415 clock-frequency = <48000000>;
1416 };
1417 };
1418
1419 target-module@32000 { /* 0x48032000, ap 5 02.0 */
1420 compatible = "ti,sysc-omap2-timer", "ti,sysc";
1421 reg = <0x32000 0x4>,
1422 <0x32010 0x4>,
1423 <0x32014 0x4>;
1424 reg-names = "rev", "sysc", "syss";
1425 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1426 SYSC_OMAP2_EMUFREE |
1427 SYSC_OMAP2_ENAWAKEUP |
1428 SYSC_OMAP2_SOFTRESET |
1429 SYSC_OMAP2_AUTOIDLE)>;
1430 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1431 <SYSC_IDLE_NO>,
1432 <SYSC_IDLE_SMART>;
1433 ti,syss-mask = <1>;
1434 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1435 clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
1436 clock-names = "fck";
1437 #address-cells = <1>;
1438 #size-cells = <1>;
1439 ranges = <0x0 0x32000 0x1000>;
1440
1441 timer2: timer@0 {
1442 compatible = "ti,omap3430-timer";
1443 reg = <0x0 0x80>;
1444 clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>;
1445 clock-names = "fck";
1446 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1447 };
1448 };
1449
1450 target-module@34000 { /* 0x48034000, ap 7 04.0 */
1451 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1452 reg = <0x34000 0x4>,
1453 <0x34010 0x4>;
1454 reg-names = "rev", "sysc";
1455 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1456 SYSC_OMAP4_SOFTRESET)>;
1457 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1458 <SYSC_IDLE_NO>,
1459 <SYSC_IDLE_SMART>,
1460 <SYSC_IDLE_SMART_WKUP>;
1461 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1462 clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
1463 clock-names = "fck";
1464 #address-cells = <1>;
1465 #size-cells = <1>;
1466 ranges = <0x0 0x34000 0x1000>;
1467
1468 timer3: timer@0 {
1469 compatible = "ti,omap4430-timer";
1470 reg = <0x0 0x80>;
1471 clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>;
1472 clock-names = "fck";
1473 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1474 };
1475 };
1476
1477 target-module@36000 { /* 0x48036000, ap 9 0e.0 */
1478 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1479 reg = <0x36000 0x4>,
1480 <0x36010 0x4>;
1481 reg-names = "rev", "sysc";
1482 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1483 SYSC_OMAP4_SOFTRESET)>;
1484 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1485 <SYSC_IDLE_NO>,
1486 <SYSC_IDLE_SMART>,
1487 <SYSC_IDLE_SMART_WKUP>;
1488 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1489 clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
1490 clock-names = "fck";
1491 #address-cells = <1>;
1492 #size-cells = <1>;
1493 ranges = <0x0 0x36000 0x1000>;
1494
1495 timer4: timer@0 {
1496 compatible = "ti,omap4430-timer";
1497 reg = <0x0 0x80>;
1498 clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>;
1499 clock-names = "fck";
1500 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1501 };
1502 };
1503
1504 target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
1505 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1506 reg = <0x3e000 0x4>,
1507 <0x3e010 0x4>;
1508 reg-names = "rev", "sysc";
1509 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1510 SYSC_OMAP4_SOFTRESET)>;
1511 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1512 <SYSC_IDLE_NO>,
1513 <SYSC_IDLE_SMART>,
1514 <SYSC_IDLE_SMART_WKUP>;
1515 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1516 clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
1517 clock-names = "fck";
1518 #address-cells = <1>;
1519 #size-cells = <1>;
1520 ranges = <0x0 0x3e000 0x1000>;
1521
1522 timer9: timer@0 {
1523 compatible = "ti,omap4430-timer";
1524 reg = <0x0 0x80>;
1525 clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
1526 clock-names = "fck";
1527 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1528 ti,timer-pwm;
1529 };
1530 };
1531
1532 /* Unused DSS L4 access, see L3 instead */
1533 target-module@40000 { /* 0x48040000, ap 13 0a.0 */
1534 compatible = "ti,sysc";
1535 status = "disabled";
1536 #address-cells = <1>;
1537 #size-cells = <1>;
1538 ranges = <0x0 0x40000 0x10000>;
1539 };
1540
1541 target-module@55000 { /* 0x48055000, ap 15 0c.0 */
1542 compatible = "ti,sysc-omap2", "ti,sysc";
1543 reg = <0x55000 0x4>,
1544 <0x55010 0x4>,
1545 <0x55114 0x4>;
1546 reg-names = "rev", "sysc", "syss";
1547 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1548 SYSC_OMAP2_SOFTRESET |
1549 SYSC_OMAP2_AUTOIDLE)>;
1550 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1551 <SYSC_IDLE_NO>,
1552 <SYSC_IDLE_SMART>,
1553 <SYSC_IDLE_SMART_WKUP>;
1554 ti,syss-mask = <1>;
1555 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1556 clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>,
1557 <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
1558 clock-names = "fck", "dbclk";
1559 #address-cells = <1>;
1560 #size-cells = <1>;
1561 ranges = <0x0 0x55000 0x1000>;
1562
1563 gpio2: gpio@0 {
1564 compatible = "ti,omap4-gpio";
1565 reg = <0x0 0x200>;
1566 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1567 gpio-controller;
1568 #gpio-cells = <2>;
1569 interrupt-controller;
1570 #interrupt-cells = <2>;
1571 };
1572 };
1573
1574 target-module@57000 { /* 0x48057000, ap 17 16.0 */
1575 compatible = "ti,sysc-omap2", "ti,sysc";
1576 reg = <0x57000 0x4>,
1577 <0x57010 0x4>,
1578 <0x57114 0x4>;
1579 reg-names = "rev", "sysc", "syss";
1580 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1581 SYSC_OMAP2_SOFTRESET |
1582 SYSC_OMAP2_AUTOIDLE)>;
1583 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1584 <SYSC_IDLE_NO>,
1585 <SYSC_IDLE_SMART>,
1586 <SYSC_IDLE_SMART_WKUP>;
1587 ti,syss-mask = <1>;
1588 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1589 clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>,
1590 <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>;
1591 clock-names = "fck", "dbclk";
1592 #address-cells = <1>;
1593 #size-cells = <1>;
1594 ranges = <0x0 0x57000 0x1000>;
1595
1596 gpio3: gpio@0 {
1597 compatible = "ti,omap4-gpio";
1598 reg = <0x0 0x200>;
1599 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1600 gpio-controller;
1601 #gpio-cells = <2>;
1602 interrupt-controller;
1603 #interrupt-cells = <2>;
1604 };
1605 };
1606
1607 target-module@59000 { /* 0x48059000, ap 19 10.0 */
1608 compatible = "ti,sysc-omap2", "ti,sysc";
1609 reg = <0x59000 0x4>,
1610 <0x59010 0x4>,
1611 <0x59114 0x4>;
1612 reg-names = "rev", "sysc", "syss";
1613 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1614 SYSC_OMAP2_SOFTRESET |
1615 SYSC_OMAP2_AUTOIDLE)>;
1616 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1617 <SYSC_IDLE_NO>,
1618 <SYSC_IDLE_SMART>,
1619 <SYSC_IDLE_SMART_WKUP>;
1620 ti,syss-mask = <1>;
1621 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1622 clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>,
1623 <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>;
1624 clock-names = "fck", "dbclk";
1625 #address-cells = <1>;
1626 #size-cells = <1>;
1627 ranges = <0x0 0x59000 0x1000>;
1628
1629 gpio4: gpio@0 {
1630 compatible = "ti,omap4-gpio";
1631 reg = <0x0 0x200>;
1632 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1633 gpio-controller;
1634 #gpio-cells = <2>;
1635 interrupt-controller;
1636 #interrupt-cells = <2>;
1637 };
1638 };
1639
1640 target-module@5b000 { /* 0x4805b000, ap 21 12.0 */
1641 compatible = "ti,sysc-omap2", "ti,sysc";
1642 reg = <0x5b000 0x4>,
1643 <0x5b010 0x4>,
1644 <0x5b114 0x4>;
1645 reg-names = "rev", "sysc", "syss";
1646 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1647 SYSC_OMAP2_SOFTRESET |
1648 SYSC_OMAP2_AUTOIDLE)>;
1649 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1650 <SYSC_IDLE_NO>,
1651 <SYSC_IDLE_SMART>,
1652 <SYSC_IDLE_SMART_WKUP>;
1653 ti,syss-mask = <1>;
1654 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1655 clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>,
1656 <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>;
1657 clock-names = "fck", "dbclk";
1658 #address-cells = <1>;
1659 #size-cells = <1>;
1660 ranges = <0x0 0x5b000 0x1000>;
1661
1662 gpio5: gpio@0 {
1663 compatible = "ti,omap4-gpio";
1664 reg = <0x0 0x200>;
1665 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1666 gpio-controller;
1667 #gpio-cells = <2>;
1668 interrupt-controller;
1669 #interrupt-cells = <2>;
1670 };
1671 };
1672
1673 target-module@5d000 { /* 0x4805d000, ap 23 14.0 */
1674 compatible = "ti,sysc-omap2", "ti,sysc";
1675 reg = <0x5d000 0x4>,
1676 <0x5d010 0x4>,
1677 <0x5d114 0x4>;
1678 reg-names = "rev", "sysc", "syss";
1679 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1680 SYSC_OMAP2_SOFTRESET |
1681 SYSC_OMAP2_AUTOIDLE)>;
1682 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1683 <SYSC_IDLE_NO>,
1684 <SYSC_IDLE_SMART>,
1685 <SYSC_IDLE_SMART_WKUP>;
1686 ti,syss-mask = <1>;
1687 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1688 clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>,
1689 <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>;
1690 clock-names = "fck", "dbclk";
1691 #address-cells = <1>;
1692 #size-cells = <1>;
1693 ranges = <0x0 0x5d000 0x1000>;
1694
1695 gpio6: gpio@0 {
1696 compatible = "ti,omap4-gpio";
1697 reg = <0x0 0x200>;
1698 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1699 gpio-controller;
1700 #gpio-cells = <2>;
1701 interrupt-controller;
1702 #interrupt-cells = <2>;
1703 };
1704 };
1705
1706 target-module@60000 { /* 0x48060000, ap 25 1e.0 */
1707 compatible = "ti,sysc-omap2", "ti,sysc";
1708 reg = <0x60000 0x8>,
1709 <0x60010 0x8>,
1710 <0x60090 0x8>;
1711 reg-names = "rev", "sysc", "syss";
1712 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1713 SYSC_OMAP2_ENAWAKEUP |
1714 SYSC_OMAP2_SOFTRESET |
1715 SYSC_OMAP2_AUTOIDLE)>;
1716 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1717 <SYSC_IDLE_NO>,
1718 <SYSC_IDLE_SMART>,
1719 <SYSC_IDLE_SMART_WKUP>;
1720 ti,syss-mask = <1>;
1721 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1722 clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
1723 clock-names = "fck";
1724 #address-cells = <1>;
1725 #size-cells = <1>;
1726 ranges = <0x0 0x60000 0x1000>;
1727
1728 i2c3: i2c@0 {
1729 compatible = "ti,omap4-i2c";
1730 reg = <0x0 0x100>;
1731 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1732 #address-cells = <1>;
1733 #size-cells = <0>;
1734 };
1735 };
1736
1737 target-module@6a000 { /* 0x4806a000, ap 26 18.0 */
1738 compatible = "ti,sysc-omap2", "ti,sysc";
1739 reg = <0x6a050 0x4>,
1740 <0x6a054 0x4>,
1741 <0x6a058 0x4>;
1742 reg-names = "rev", "sysc", "syss";
1743 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1744 SYSC_OMAP2_SOFTRESET |
1745 SYSC_OMAP2_AUTOIDLE)>;
1746 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1747 <SYSC_IDLE_NO>,
1748 <SYSC_IDLE_SMART>,
1749 <SYSC_IDLE_SMART_WKUP>;
1750 ti,syss-mask = <1>;
1751 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1752 clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
1753 clock-names = "fck";
1754 #address-cells = <1>;
1755 #size-cells = <1>;
1756 ranges = <0x0 0x6a000 0x1000>;
1757
1758 uart1: serial@0 {
1759 compatible = "ti,omap4-uart";
1760 reg = <0x0 0x100>;
1761 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1762 clock-frequency = <48000000>;
1763 };
1764 };
1765
1766 target-module@6c000 { /* 0x4806c000, ap 28 20.0 */
1767 compatible = "ti,sysc-omap2", "ti,sysc";
1768 reg = <0x6c050 0x4>,
1769 <0x6c054 0x4>,
1770 <0x6c058 0x4>;
1771 reg-names = "rev", "sysc", "syss";
1772 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1773 SYSC_OMAP2_SOFTRESET |
1774 SYSC_OMAP2_AUTOIDLE)>;
1775 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1776 <SYSC_IDLE_NO>,
1777 <SYSC_IDLE_SMART>,
1778 <SYSC_IDLE_SMART_WKUP>;
1779 ti,syss-mask = <1>;
1780 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1781 clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
1782 clock-names = "fck";
1783 #address-cells = <1>;
1784 #size-cells = <1>;
1785 ranges = <0x0 0x6c000 0x1000>;
1786
1787 uart2: serial@0 {
1788 compatible = "ti,omap4-uart";
1789 reg = <0x0 0x100>;
1790 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1791 clock-frequency = <48000000>;
1792 };
1793 };
1794
1795 target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */
1796 compatible = "ti,sysc-omap2", "ti,sysc";
1797 reg = <0x6e050 0x4>,
1798 <0x6e054 0x4>,
1799 <0x6e058 0x4>;
1800 reg-names = "rev", "sysc", "syss";
1801 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1802 SYSC_OMAP2_SOFTRESET |
1803 SYSC_OMAP2_AUTOIDLE)>;
1804 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1805 <SYSC_IDLE_NO>,
1806 <SYSC_IDLE_SMART>,
1807 <SYSC_IDLE_SMART_WKUP>;
1808 ti,syss-mask = <1>;
1809 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1810 clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
1811 clock-names = "fck";
1812 #address-cells = <1>;
1813 #size-cells = <1>;
1814 ranges = <0x0 0x6e000 0x1000>;
1815
1816 uart4: serial@0 {
1817 compatible = "ti,omap4-uart";
1818 reg = <0x0 0x100>;
1819 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1820 clock-frequency = <48000000>;
1821 };
1822 };
1823
1824 target-module@70000 { /* 0x48070000, ap 32 28.0 */
1825 compatible = "ti,sysc-omap2", "ti,sysc";
1826 reg = <0x70000 0x8>,
1827 <0x70010 0x8>,
1828 <0x70090 0x8>;
1829 reg-names = "rev", "sysc", "syss";
1830 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1831 SYSC_OMAP2_ENAWAKEUP |
1832 SYSC_OMAP2_SOFTRESET |
1833 SYSC_OMAP2_AUTOIDLE)>;
1834 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1835 <SYSC_IDLE_NO>,
1836 <SYSC_IDLE_SMART>,
1837 <SYSC_IDLE_SMART_WKUP>;
1838 ti,syss-mask = <1>;
1839 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1840 clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
1841 clock-names = "fck";
1842 #address-cells = <1>;
1843 #size-cells = <1>;
1844 ranges = <0x0 0x70000 0x1000>;
1845
1846 i2c1: i2c@0 {
1847 compatible = "ti,omap4-i2c";
1848 reg = <0x0 0x100>;
1849 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cells = <1>;
1851 #size-cells = <0>;
1852 };
1853 };
1854
1855 target-module@72000 { /* 0x48072000, ap 34 30.0 */
1856 compatible = "ti,sysc-omap2", "ti,sysc";
1857 reg = <0x72000 0x8>,
1858 <0x72010 0x8>,
1859 <0x72090 0x8>;
1860 reg-names = "rev", "sysc", "syss";
1861 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1862 SYSC_OMAP2_ENAWAKEUP |
1863 SYSC_OMAP2_SOFTRESET |
1864 SYSC_OMAP2_AUTOIDLE)>;
1865 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1866 <SYSC_IDLE_NO>,
1867 <SYSC_IDLE_SMART>,
1868 <SYSC_IDLE_SMART_WKUP>;
1869 ti,syss-mask = <1>;
1870 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1871 clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
1872 clock-names = "fck";
1873 #address-cells = <1>;
1874 #size-cells = <1>;
1875 ranges = <0x0 0x72000 0x1000>;
1876
1877 i2c2: i2c@0 {
1878 compatible = "ti,omap4-i2c";
1879 reg = <0x0 0x100>;
1880 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1881 #address-cells = <1>;
1882 #size-cells = <0>;
1883 };
1884 };
1885
1886 target-module@76000 { /* 0x48076000, ap 39 38.0 */
1887 compatible = "ti,sysc-omap4", "ti,sysc";
1888 reg = <0x76000 0x4>,
1889 <0x76010 0x4>;
1890 reg-names = "rev", "sysc";
1891 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1892 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1893 <SYSC_IDLE_NO>,
1894 <SYSC_IDLE_SMART>,
1895 <SYSC_IDLE_SMART_WKUP>;
1896 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1897 clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>;
1898 clock-names = "fck";
1899 #address-cells = <1>;
1900 #size-cells = <1>;
1901 ranges = <0x0 0x76000 0x1000>;
1902
1903 /* No child device binding or driver in mainline */
1904 };
1905
1906 target-module@78000 { /* 0x48078000, ap 41 1a.0 */
1907 compatible = "ti,sysc-omap2", "ti,sysc";
1908 reg = <0x78000 0x4>,
1909 <0x78010 0x4>,
1910 <0x78014 0x4>;
1911 reg-names = "rev", "sysc", "syss";
1912 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1913 SYSC_OMAP2_SOFTRESET |
1914 SYSC_OMAP2_AUTOIDLE)>;
1915 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1916 <SYSC_IDLE_NO>,
1917 <SYSC_IDLE_SMART>;
1918 ti,syss-mask = <1>;
1919 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1920 clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
1921 clock-names = "fck";
1922 #address-cells = <1>;
1923 #size-cells = <1>;
1924 ranges = <0x0 0x78000 0x1000>;
1925
1926 elm: elm@0 {
1927 compatible = "ti,am3352-elm";
1928 reg = <0x0 0x2000>;
1929 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1930 status = "disabled";
1931 };
1932 };
1933
1934 target-module@86000 { /* 0x48086000, ap 43 24.0 */
1935 compatible = "ti,sysc-omap2-timer", "ti,sysc";
1936 reg = <0x86000 0x4>,
1937 <0x86010 0x4>,
1938 <0x86014 0x4>;
1939 reg-names = "rev", "sysc", "syss";
1940 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1941 SYSC_OMAP2_EMUFREE |
1942 SYSC_OMAP2_ENAWAKEUP |
1943 SYSC_OMAP2_SOFTRESET |
1944 SYSC_OMAP2_AUTOIDLE)>;
1945 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1946 <SYSC_IDLE_NO>,
1947 <SYSC_IDLE_SMART>;
1948 ti,syss-mask = <1>;
1949 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1950 clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
1951 clock-names = "fck";
1952 #address-cells = <1>;
1953 #size-cells = <1>;
1954 ranges = <0x0 0x86000 0x1000>;
1955
1956 timer10: timer@0 {
1957 compatible = "ti,omap3430-timer";
1958 reg = <0x0 0x80>;
1959 clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>;
1960 clock-names = "fck";
1961 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1962 ti,timer-pwm;
1963 };
1964 };
1965
1966 target-module@88000 { /* 0x48088000, ap 45 2e.0 */
1967 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1968 reg = <0x88000 0x4>,
1969 <0x88010 0x4>;
1970 reg-names = "rev", "sysc";
1971 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1972 SYSC_OMAP4_SOFTRESET)>;
1973 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1974 <SYSC_IDLE_NO>,
1975 <SYSC_IDLE_SMART>,
1976 <SYSC_IDLE_SMART_WKUP>;
1977 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1978 clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
1979 clock-names = "fck";
1980 #address-cells = <1>;
1981 #size-cells = <1>;
1982 ranges = <0x0 0x88000 0x1000>;
1983
1984 timer11: timer@0 {
1985 compatible = "ti,omap4430-timer";
1986 reg = <0x0 0x80>;
1987 clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>;
1988 clock-names = "fck";
1989 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1990 ti,timer-pwm;
1991 };
1992 };
1993
1994 rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
1995 compatible = "ti,sysc-omap2", "ti,sysc";
1996 reg = <0x91fe0 0x4>,
1997 <0x91fe4 0x4>;
1998 reg-names = "rev", "sysc";
1999 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
2000 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2001 <SYSC_IDLE_NO>;
2002 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
2003 clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
2004 clock-names = "fck";
2005 #address-cells = <1>;
2006 #size-cells = <1>;
2007 ranges = <0x0 0x90000 0x2000>;
2008
2009 rng: rng@0 {
2010 compatible = "ti,omap4-rng";
2011 reg = <0x0 0x2000>;
2012 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
2013 };
2014 };
2015
2016 target-module@96000 { /* 0x48096000, ap 37 26.0 */
2017 compatible = "ti,sysc-omap2", "ti,sysc";
2018 reg = <0x9608c 0x4>;
2019 reg-names = "sysc";
2020 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
2021 SYSC_OMAP2_ENAWAKEUP |
2022 SYSC_OMAP2_SOFTRESET)>;
2023 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2024 <SYSC_IDLE_NO>,
2025 <SYSC_IDLE_SMART>;
2026 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2027 clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
2028 clock-names = "fck";
2029 #address-cells = <1>;
2030 #size-cells = <1>;
2031 ranges = <0x0 0x96000 0x1000>;
2032
2033 mcbsp4: mcbsp@0 {
2034 compatible = "ti,omap4-mcbsp";
2035 reg = <0x0 0xff>; /* L4 Interconnect */
2036 reg-names = "mpu";
2037 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2038 interrupt-names = "common";
2039 ti,buffer-size = <128>;
2040 dmas = <&sdma 31>,
2041 <&sdma 32>;
2042 dma-names = "tx", "rx";
2043 status = "disabled";
2044 };
2045 };
2046
2047 target-module@98000 { /* 0x48098000, ap 49 22.0 */
2048 compatible = "ti,sysc-omap4", "ti,sysc";
2049 reg = <0x98000 0x4>,
2050 <0x98010 0x4>;
2051 reg-names = "rev", "sysc";
2052 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2053 SYSC_OMAP4_SOFTRESET)>;
2054 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2055 <SYSC_IDLE_NO>,
2056 <SYSC_IDLE_SMART>,
2057 <SYSC_IDLE_SMART_WKUP>;
2058 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2059 clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
2060 clock-names = "fck";
2061 #address-cells = <1>;
2062 #size-cells = <1>;
2063 ranges = <0x0 0x98000 0x1000>;
2064
2065 mcspi1: spi@0 {
2066 compatible = "ti,omap4-mcspi";
2067 reg = <0x0 0x200>;
2068 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
2069 #address-cells = <1>;
2070 #size-cells = <0>;
2071 ti,spi-num-cs = <4>;
2072 dmas = <&sdma 35>,
2073 <&sdma 36>,
2074 <&sdma 37>,
2075 <&sdma 38>,
2076 <&sdma 39>,
2077 <&sdma 40>,
2078 <&sdma 41>,
2079 <&sdma 42>;
2080 dma-names = "tx0", "rx0", "tx1", "rx1",
2081 "tx2", "rx2", "tx3", "rx3";
2082 };
2083 };
2084
2085 target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
2086 compatible = "ti,sysc-omap4", "ti,sysc";
2087 reg = <0x9a000 0x4>,
2088 <0x9a010 0x4>;
2089 reg-names = "rev", "sysc";
2090 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2091 SYSC_OMAP4_SOFTRESET)>;
2092 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2093 <SYSC_IDLE_NO>,
2094 <SYSC_IDLE_SMART>,
2095 <SYSC_IDLE_SMART_WKUP>;
2096 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2097 clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
2098 clock-names = "fck";
2099 #address-cells = <1>;
2100 #size-cells = <1>;
2101 ranges = <0x0 0x9a000 0x1000>;
2102
2103 mcspi2: spi@0 {
2104 compatible = "ti,omap4-mcspi";
2105 reg = <0x0 0x200>;
2106 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
2107 #address-cells = <1>;
2108 #size-cells = <0>;
2109 ti,spi-num-cs = <2>;
2110 dmas = <&sdma 43>,
2111 <&sdma 44>,
2112 <&sdma 45>,
2113 <&sdma 46>;
2114 dma-names = "tx0", "rx0", "tx1", "rx1";
2115 };
2116 };
2117
2118 target-module@9c000 { /* 0x4809c000, ap 53 36.0 */
2119 compatible = "ti,sysc-omap4", "ti,sysc";
2120 reg = <0x9c000 0x4>,
2121 <0x9c010 0x4>;
2122 reg-names = "rev", "sysc";
2123 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2124 SYSC_OMAP4_SOFTRESET)>;
2125 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2126 <SYSC_IDLE_NO>,
2127 <SYSC_IDLE_SMART>,
2128 <SYSC_IDLE_SMART_WKUP>;
2129 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2130 <SYSC_IDLE_NO>,
2131 <SYSC_IDLE_SMART>,
2132 <SYSC_IDLE_SMART_WKUP>;
2133 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
2134 clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
2135 clock-names = "fck";
2136 #address-cells = <1>;
2137 #size-cells = <1>;
2138 ranges = <0x0 0x9c000 0x1000>;
2139
2140 mmc1: mmc@0 {
2141 compatible = "ti,omap4-hsmmc";
2142 reg = <0x0 0x400>;
2143 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2144 ti,dual-volt;
2145 ti,needs-special-reset;
2146 dmas = <&sdma 61>, <&sdma 62>;
2147 dma-names = "tx", "rx";
2148 pbias-supply = <&pbias_mmc_reg>;
2149 };
2150 };
2151
2152 target-module@9e000 { /* 0x4809e000, ap 55 48.0 */
2153 compatible = "ti,sysc";
2154 status = "disabled";
2155 #address-cells = <1>;
2156 #size-cells = <1>;
2157 ranges = <0x0 0x9e000 0x1000>;
2158 };
2159
2160 target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */
2161 compatible = "ti,sysc";
2162 status = "disabled";
2163 #address-cells = <1>;
2164 #size-cells = <1>;
2165 ranges = <0x0 0xa2000 0x1000>;
2166 };
2167
2168 target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
2169 compatible = "ti,sysc";
2170 status = "disabled";
2171 #address-cells = <1>;
2172 #size-cells = <1>;
2173 ranges = <0x00000000 0x000a4000 0x00001000>,
2174 <0x00001000 0x000a5000 0x00001000>;
2175 };
2176
2177 des_target: target-module@a5000 { /* 0x480a5000 */
2178 compatible = "ti,sysc-omap2", "ti,sysc";
2179 reg = <0xa5030 0x4>,
2180 <0xa5034 0x4>,
2181 <0xa5038 0x4>;
2182 reg-names = "rev", "sysc", "syss";
2183 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2184 SYSC_OMAP2_AUTOIDLE)>;
2185 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2186 <SYSC_IDLE_NO>,
2187 <SYSC_IDLE_SMART>,
2188 <SYSC_IDLE_SMART_WKUP>;
2189 ti,syss-mask = <1>;
2190 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
2191 clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
2192 clock-names = "fck";
2193 #address-cells = <1>;
2194 #size-cells = <1>;
2195 ranges = <0 0xa5000 0x00001000>;
2196
2197 des: des@0 {
2198 compatible = "ti,omap4-des";
2199 reg = <0 0xa0>;
2200 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
2201 dmas = <&sdma 117>, <&sdma 116>;
2202 dma-names = "tx", "rx";
2203 };
2204 };
2205
2206 target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
2207 compatible = "ti,sysc";
2208 status = "disabled";
2209 #address-cells = <1>;
2210 #size-cells = <1>;
2211 ranges = <0x0 0xa8000 0x4000>;
2212 };
2213
2214 target-module@ad000 { /* 0x480ad000, ap 63 50.0 */
2215 compatible = "ti,sysc-omap4", "ti,sysc";
2216 reg = <0xad000 0x4>,
2217 <0xad010 0x4>;
2218 reg-names = "rev", "sysc";
2219 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2220 SYSC_OMAP4_SOFTRESET)>;
2221 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2222 <SYSC_IDLE_NO>,
2223 <SYSC_IDLE_SMART>,
2224 <SYSC_IDLE_SMART_WKUP>;
2225 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2226 <SYSC_IDLE_NO>,
2227 <SYSC_IDLE_SMART>,
2228 <SYSC_IDLE_SMART_WKUP>;
2229 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2230 clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
2231 clock-names = "fck";
2232 #address-cells = <1>;
2233 #size-cells = <1>;
2234 ranges = <0x0 0xad000 0x1000>;
2235
2236 mmc3: mmc@0 {
2237 compatible = "ti,omap4-hsmmc";
2238 reg = <0x0 0x400>;
2239 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
2240 ti,needs-special-reset;
2241 dmas = <&sdma 77>, <&sdma 78>;
2242 dma-names = "tx", "rx";
2243 };
2244 };
2245
2246 target-module@b0000 { /* 0x480b0000, ap 47 40.0 */
2247 compatible = "ti,sysc";
2248 status = "disabled";
2249 #address-cells = <1>;
2250 #size-cells = <1>;
2251 ranges = <0x0 0xb0000 0x1000>;
2252 };
2253
2254 target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */
2255 compatible = "ti,sysc-omap2", "ti,sysc";
2256 reg = <0xb2000 0x4>,
2257 <0xb2014 0x4>,
2258 <0xb2018 0x4>;
2259 reg-names = "rev", "sysc", "syss";
2260 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2261 SYSC_OMAP2_AUTOIDLE)>;
2262 ti,syss-mask = <1>;
2263 ti,no-reset-on-init;
2264 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2265 clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>;
2266 clock-names = "fck";
2267 #address-cells = <1>;
2268 #size-cells = <1>;
2269 ranges = <0x0 0xb2000 0x1000>;
2270
2271 hdqw1w: 1w@0 {
2272 compatible = "ti,omap3-1w";
2273 reg = <0x0 0x1000>;
2274 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
2275 };
2276 };
2277
2278 target-module@b4000 { /* 0x480b4000, ap 67 46.0 */
2279 compatible = "ti,sysc-omap4", "ti,sysc";
2280 reg = <0xb4000 0x4>,
2281 <0xb4010 0x4>;
2282 reg-names = "rev", "sysc";
2283 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2284 SYSC_OMAP4_SOFTRESET)>;
2285 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2286 <SYSC_IDLE_NO>,
2287 <SYSC_IDLE_SMART>,
2288 <SYSC_IDLE_SMART_WKUP>;
2289 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2290 <SYSC_IDLE_NO>,
2291 <SYSC_IDLE_SMART>,
2292 <SYSC_IDLE_SMART_WKUP>;
2293 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
2294 clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
2295 clock-names = "fck";
2296 #address-cells = <1>;
2297 #size-cells = <1>;
2298 ranges = <0x0 0xb4000 0x1000>;
2299
2300 mmc2: mmc@0 {
2301 compatible = "ti,omap4-hsmmc";
2302 reg = <0x0 0x400>;
2303 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2304 ti,needs-special-reset;
2305 dmas = <&sdma 47>, <&sdma 48>;
2306 dma-names = "tx", "rx";
2307 };
2308 };
2309
2310 target-module@b8000 { /* 0x480b8000, ap 69 58.0 */
2311 compatible = "ti,sysc-omap4", "ti,sysc";
2312 reg = <0xb8000 0x4>,
2313 <0xb8010 0x4>;
2314 reg-names = "rev", "sysc";
2315 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2316 SYSC_OMAP4_SOFTRESET)>;
2317 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2318 <SYSC_IDLE_NO>,
2319 <SYSC_IDLE_SMART>,
2320 <SYSC_IDLE_SMART_WKUP>;
2321 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2322 clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
2323 clock-names = "fck";
2324 #address-cells = <1>;
2325 #size-cells = <1>;
2326 ranges = <0x0 0xb8000 0x1000>;
2327
2328 mcspi3: spi@0 {
2329 compatible = "ti,omap4-mcspi";
2330 reg = <0x0 0x200>;
2331 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2332 #address-cells = <1>;
2333 #size-cells = <0>;
2334 ti,spi-num-cs = <2>;
2335 dmas = <&sdma 15>, <&sdma 16>;
2336 dma-names = "tx0", "rx0";
2337 };
2338 };
2339
2340 target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
2341 compatible = "ti,sysc-omap4", "ti,sysc";
2342 reg = <0xba000 0x4>,
2343 <0xba010 0x4>;
2344 reg-names = "rev", "sysc";
2345 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2346 SYSC_OMAP4_SOFTRESET)>;
2347 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2348 <SYSC_IDLE_NO>,
2349 <SYSC_IDLE_SMART>,
2350 <SYSC_IDLE_SMART_WKUP>;
2351 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2352 clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
2353 clock-names = "fck";
2354 #address-cells = <1>;
2355 #size-cells = <1>;
2356 ranges = <0x0 0xba000 0x1000>;
2357
2358 mcspi4: spi@0 {
2359 compatible = "ti,omap4-mcspi";
2360 reg = <0x0 0x200>;
2361 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
2362 #address-cells = <1>;
2363 #size-cells = <0>;
2364 ti,spi-num-cs = <1>;
2365 dmas = <&sdma 70>, <&sdma 71>;
2366 dma-names = "tx0", "rx0";
2367 };
2368 };
2369
2370 target-module@d1000 { /* 0x480d1000, ap 73 44.0 */
2371 compatible = "ti,sysc-omap4", "ti,sysc";
2372 reg = <0xd1000 0x4>,
2373 <0xd1010 0x4>;
2374 reg-names = "rev", "sysc";
2375 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2376 SYSC_OMAP4_SOFTRESET)>;
2377 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2378 <SYSC_IDLE_NO>,
2379 <SYSC_IDLE_SMART>,
2380 <SYSC_IDLE_SMART_WKUP>;
2381 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2382 <SYSC_IDLE_NO>,
2383 <SYSC_IDLE_SMART>,
2384 <SYSC_IDLE_SMART_WKUP>;
2385 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2386 clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
2387 clock-names = "fck";
2388 #address-cells = <1>;
2389 #size-cells = <1>;
2390 ranges = <0x0 0xd1000 0x1000>;
2391
2392 mmc4: mmc@0 {
2393 compatible = "ti,omap4-hsmmc";
2394 reg = <0x0 0x400>;
2395 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2396 ti,needs-special-reset;
2397 dmas = <&sdma 57>, <&sdma 58>;
2398 dma-names = "tx", "rx";
2399 };
2400 };
2401
2402 target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */
2403 compatible = "ti,sysc-omap4", "ti,sysc";
2404 reg = <0xd5000 0x4>,
2405 <0xd5010 0x4>;
2406 reg-names = "rev", "sysc";
2407 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2408 SYSC_OMAP4_SOFTRESET)>;
2409 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2410 <SYSC_IDLE_NO>,
2411 <SYSC_IDLE_SMART>,
2412 <SYSC_IDLE_SMART_WKUP>;
2413 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2414 <SYSC_IDLE_NO>,
2415 <SYSC_IDLE_SMART>,
2416 <SYSC_IDLE_SMART_WKUP>;
2417 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2418 clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
2419 clock-names = "fck";
2420 #address-cells = <1>;
2421 #size-cells = <1>;
2422 ranges = <0x0 0xd5000 0x1000>;
2423
2424 mmc5: mmc@0 {
2425 compatible = "ti,omap4-hsmmc";
2426 reg = <0x0 0x400>;
2427 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
2428 ti,needs-special-reset;
2429 dmas = <&sdma 59>, <&sdma 60>;
2430 dma-names = "tx", "rx";
2431 };
2432 };
2433 };
2434
2435 segment@200000 { /* 0x48200000 */
2436 compatible = "simple-bus";
2437 #address-cells = <1>;
2438 #size-cells = <1>;
2439 ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */
2440 <0x00151000 0x00351000 0x001000>; /* ap 78 */
2441
2442 target-module@150000 { /* 0x48350000, ap 77 4c.0 */
2443 compatible = "ti,sysc-omap2", "ti,sysc";
2444 reg = <0x150000 0x8>,
2445 <0x150010 0x8>,
2446 <0x150090 0x8>;
2447 reg-names = "rev", "sysc", "syss";
2448 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
2449 SYSC_OMAP2_ENAWAKEUP |
2450 SYSC_OMAP2_SOFTRESET |
2451 SYSC_OMAP2_AUTOIDLE)>;
2452 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2453 <SYSC_IDLE_NO>,
2454 <SYSC_IDLE_SMART>,
2455 <SYSC_IDLE_SMART_WKUP>;
2456 ti,syss-mask = <1>;
2457 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2458 clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
2459 clock-names = "fck";
2460 #address-cells = <1>;
2461 #size-cells = <1>;
2462 ranges = <0x0 0x150000 0x1000>;
2463
2464 i2c4: i2c@0 {
2465 compatible = "ti,omap4-i2c";
2466 reg = <0x0 0x100>;
2467 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
2468 #address-cells = <1>;
2469 #size-cells = <0>;
2470 };
2471 };
2472 };
2473};