blob: f24d3a4b1cd95eec0884111238bd2a467bf6cc35 [file] [log] [blame]
Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
2 * Copyright 2004 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 * Change log:
23 *
24 * 20050101: Eran Liberty (liberty@freescale.com)
Wolfgang Denk07a25052005-08-05 19:49:35 +020025 * Initial file creating (porting from 85XX & 8260)
Eran Libertyf046ccd2005-07-28 10:08:46 -050026 */
27
28/*
29 * CPU specific code for the MPC83xx family.
30 *
31 * Derived from the MPC8260 and MPC85xx.
32 */
33
34#include <common.h>
35#include <watchdog.h>
36#include <command.h>
37#include <mpc83xx.h>
Kumar Gala62ec6412006-01-11 16:48:10 -060038#include <ft_build.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050039#include <asm/processor.h>
40
41
42int checkcpu(void)
43{
44 DECLARE_GLOBAL_DATA_PTR;
45 ulong clock = gd->cpu_clk;
46 u32 pvr = get_pvr();
47 char buf[32];
48
49 if ((pvr & 0xFFFF0000) != PVR_83xx) {
50 puts("Not MPC83xx Family!!!\n");
51 return -1;
52 }
53
Marian Balakowicze6f2e902005-10-11 19:09:42 +020054 puts("CPU: MPC83xx, ");
Eran Libertyf046ccd2005-07-28 10:08:46 -050055 switch(pvr) {
56 case PVR_8349_REV10:
57 break;
58 case PVR_8349_REV11:
59 break;
60 default:
61 puts("Rev: Unknown\n");
62 return -1; /* Not sure what this is */
63 }
Rafal Jaworowski6902df52005-10-17 02:39:53 +020064 printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4,
65 (pvr & 0x0f), strmhz(buf, clock));
66
Eran Libertyf046ccd2005-07-28 10:08:46 -050067 return 0;
68}
69
70
71void upmconfig (uint upm, uint *table, uint size)
72{
73 hang(); /* FIXME: upconfig() needed? */
74}
75
76
77int
78do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
79{
Wolfgang Denk07a25052005-08-05 19:49:35 +020080 ulong msr;
81#ifndef MPC83xx_RESET
82 ulong addr;
83#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -050084
85 volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
86
87#ifdef MPC83xx_RESET
88 /* Interrupts and MMU off */
89 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
90
91 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
92 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
93
94 /* enable Reset Control Reg */
95 immap->reset.rpr = 0x52535445;
Marian Balakowicz6d8ae5a2006-03-14 16:12:48 +010096 __asm__ __volatile__ ("sync");
97 __asm__ __volatile__ ("isync");
Eran Libertyf046ccd2005-07-28 10:08:46 -050098
99 /* confirm Reset Control Reg is enabled */
100 while(!((immap->reset.rcer) & RCER_CRE));
101
102 printf("Resetting the board.");
103 printf("\n");
104
105 udelay(200);
106
107 /* perform reset, only one bit */
Wolfgang Denk07a25052005-08-05 19:49:35 +0200108 immap->reset.rcr = RCR_SWHR;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500109
Wolfgang Denk07a25052005-08-05 19:49:35 +0200110#else /* ! MPC83xx_RESET */
111
112 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
113
114 /* Interrupts and MMU off */
115 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500116
117 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
118 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
119
120 /*
121 * Trying to execute the next instruction at a non-existing address
122 * should cause a machine check, resulting in reset
123 */
124 addr = CFG_RESET_ADDRESS;
125
126 printf("resetting the board.");
127 printf("\n");
128 ((void (*)(void)) addr) ();
Wolfgang Denk07a25052005-08-05 19:49:35 +0200129#endif /* MPC83xx_RESET */
130
Eran Libertyf046ccd2005-07-28 10:08:46 -0500131 return 1;
132}
133
134
135/*
136 * Get timebase clock frequency (like cpu_clk in Hz)
137 */
138
139unsigned long get_tbclk(void)
140{
141 DECLARE_GLOBAL_DATA_PTR;
142
143 ulong tbclk;
144
145 tbclk = (gd->bus_clk + 3L) / 4L;
146
147 return tbclk;
148}
149
150
151#if defined(CONFIG_WATCHDOG)
152void watchdog_reset (void)
153{
154 hang(); /* FIXME: implement watchdog_reset()? */
155}
156#endif /* CONFIG_WATCHDOG */
Kumar Gala62ec6412006-01-11 16:48:10 -0600157
158#if defined(CONFIG_OF_FLAT_TREE)
159void
160ft_cpu_setup(void *blob, bd_t *bd)
161{
162 u32 *p;
163 int len;
164 ulong clock;
165
166 clock = bd->bi_busfreq;
167 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
168 if (p != NULL)
169 *p = cpu_to_be32(clock);
170
171 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
172 if (p != NULL)
173 *p = cpu_to_be32(clock);
174
175 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
176 if (p != NULL)
177 *p = cpu_to_be32(clock);
178
179 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
180 if (p != NULL)
181 *p = cpu_to_be32(clock);
182
183#ifdef CONFIG_MPC83XX_TSEC1
184 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
185 memcpy(p, bd->bi_enetaddr, 6);
186#endif
187
188#ifdef CONFIG_MPC83XX_TSEC2
189 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
190 memcpy(p, bd->bi_enet1addr, 6);
191#endif
192}
193#endif
Marian Balakowicz61f25152006-03-14 16:14:48 +0100194
195#if defined(CONFIG_DDR_ECC)
196void dma_init(void)
197{
198 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
199 volatile dma8349_t *dma = &immap->dma;
200 volatile u32 status = swab32(dma->dmasr0);
201 volatile u32 dmamr0 = swab32(dma->dmamr0);
202
203 debug("DMA-init\n");
204
205 /* initialize DMASARn, DMADAR and DMAABCRn */
206 dma->dmadar0 = (u32)0;
207 dma->dmasar0 = (u32)0;
208 dma->dmabcr0 = 0;
209
210 __asm__ __volatile__ ("sync");
211 __asm__ __volatile__ ("isync");
212
213 /* clear CS bit */
214 dmamr0 &= ~DMA_CHANNEL_START;
215 dma->dmamr0 = swab32(dmamr0);
216 __asm__ __volatile__ ("sync");
217 __asm__ __volatile__ ("isync");
218
219 /* while the channel is busy, spin */
220 while(status & DMA_CHANNEL_BUSY) {
221 status = swab32(dma->dmasr0);
222 }
223
224 debug("DMA-init end\n");
225}
226
227uint dma_check(void)
228{
229 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
230 volatile dma8349_t *dma = &immap->dma;
231 volatile u32 status = swab32(dma->dmasr0);
232 volatile u32 byte_count = swab32(dma->dmabcr0);
233
234 /* while the channel is busy, spin */
235 while (status & DMA_CHANNEL_BUSY) {
236 status = swab32(dma->dmasr0);
237 }
238
239 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
240 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
241 }
242
243 return status;
244}
245
246int dma_xfer(void *dest, u32 count, void *src)
247{
248 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
249 volatile dma8349_t *dma = &immap->dma;
250 volatile u32 dmamr0;
251
252 /* initialize DMASARn, DMADAR and DMAABCRn */
253 dma->dmadar0 = swab32((u32)dest);
254 dma->dmasar0 = swab32((u32)src);
255 dma->dmabcr0 = swab32(count);
256
257 __asm__ __volatile__ ("sync");
258 __asm__ __volatile__ ("isync");
259
260 /* init direct transfer, clear CS bit */
261 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
262 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
263 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
264
265 dma->dmamr0 = swab32(dmamr0);
266
267 __asm__ __volatile__ ("sync");
268 __asm__ __volatile__ ("isync");
269
270 /* set CS to start DMA transfer */
271 dmamr0 |= DMA_CHANNEL_START;
272 dma->dmamr0 = swab32(dmamr0);
273 __asm__ __volatile__ ("sync");
274 __asm__ __volatile__ ("isync");
275
276 return ((int)dma_check());
277}
278#endif /*CONFIG_DDR_ECC*/